CMOS delay line having duty cycle control

Details CMOS delay line having duty cycle control CMOS delay line having duty cycle control

1992-09-18

1993-07-27

Ng, Jin F.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307263, 307265, 307602, H03K 512, H03K 3017, H03K 513

Patent

active

052313204

ABSTRACT:
A delay line having feedback from a control circuit at the output of the delay line controls the delay line duty cycle to within a specified range. The delay line comprises at least one delay unit having control inputs to each delay unit. The output of the delay line feeds to a low-pass filter (LPF). A voltage proportional to the duty cycle of the delay line output is generated within the LPF and fed to a differential amplifier. The differential amplifier is in turn coupled to the control inputs of each of the delay units. When the voltage signal from the LPF is high (duty cycle is high), the differential amplifier will generate a signal causing the fall time of the signal propagating through the delay line to increase and rise time to decrease. This will decrease the high cycle time at the output of the delay line. When the voltage signal from the LPF is low (duty cycle is low), the differential amplifier will generate a signal causing the fall time to decrease and the rise time to increase. This will increase the high cycle time at the output of the delay line.

REFERENCES:
patent: 3024417 (1962-03-01), Secretan
patent: 3735270 (1973-05-01), Holub
patent: 4585952 (1986-04-01), Yamamoto
patent: 4899071 (1990-02-01), Morales
patent: 4922141 (1990-05-01), Lofgren et al.

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