CMOS delay circuit with controllable delay

Details CMOS delay circuit with controllable delay CMOS delay circuit with controllable delay

1991-03-05

1992-06-09

Laroche, Eugene R.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307606, 328 55, H03K 513, H03K 19091

Patent

active

051210142

ABSTRACT:
A variable delay circuit consists of a single-stage CMOS delay circuit having an associated time delay between its input and output. A first transistor connects a voltage supply node to other portions of the single-stage CMOS delay circuit. The impedance of the first transistor corresponds to an associated time delay. A second transistor, gated by a control signal, connects the voltage supply node and the other portions of the single-stage CMOS delay circuit in parallel with the first P-channel transistor. The delay circuit delays signals for a longer period of time when the second transistor is disabled by said control signal than when the second transistor is enabled. In a variation on this delay circuit, a plurality of delay control elements are coupled to the single-stage delay circuit, each accepting a distinct control signal and decreasing the delay circuits associated time delay to a corresponding shorter delay time when its control signal is enabled. This delay circuit delays signals by a multiplicity of distinct delay times in accordance with the control signals. Further variability in the delay time can be achieved by cascading a plurality of delay stages, with two or more of the said cascaded delay stages comprising a variable delay circuit with a delay time that is governed by one or more control signals. A multiplicity of different delay times can be selected via the control signals for the various variable delay stages.

REFERENCES:
patent: 4947064 (1990-08-01), Kim et al.
patent: 5012141 (1991-04-01), Tomisawa
patent: 5012142 (1991-04-01), Sonntag
IBM Technical Disclosure Bulletin, vol. 31, No. 1, Jun. 1988 pp. 21-23.

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