CMOS decoder circuit resistant to latch-up

Details CMOS decoder circuit resistant to latch-up CMOS decoder circuit resistant to latch-up

1986-12-12

1988-02-09

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307469, 307243, H03K 1756, H03K 19094, G06F 738

Patent

active

047243414

ABSTRACT:
A decoder part is formed by a main decoder part C and a plurality of subdecoder parts D.sub.0 to D.sub.3 connected with the main decoder part C, and a plurality of such decoder parts are provided. In such structure, the main decoder part specifies one of a plurality of decoder parts and a CMOS circuit (PMOS transistor T.sub.0 and NMOS transistors T.sub.0 ', . . . , PMOS transistor and NMOS transistor T.sub.3 ') specifies one of the subdecoder parts and PMOS transistors (T.sub.00 to T.sub.03, . . . , T.sub.30 to T.sub.33) select finally decoded output.

REFERENCES:
patent: 4651031 (1987-03-01), Kamuro
IBM Tech. Disc. Bul., "Multiple Partitioned Programmable Logic Array", Greenspan.

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