CMOS DAC with high impedance differential current drivers

Details CMOS DAC with high impedance differential current drivers CMOS DAC with high impedance differential current drivers

1999-08-25

2001-09-25

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S144000, C341S133000

Reexamination Certificate

active

06295012

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electronic devices and in particular, to those employing digital-to-analog conversion circuitry.
2. Description of Related Art
Modern electronic systems are typically realized as a complete “system on a chip.” Such systems typically integrate analog and digital functionality onto the die of a single integrated circuit. Such systems offer lower cost, power, and size benefits to the customer.
Often a system will be based on a digital signal processing (DSP) core that implements system functionality through the use of discrete mathematical algorithms that are realized through hardware, firmware, or programmable means. In order for the system to interface to analog based continuous signals, such systems typically employ the use of a digital-to-analog converter (DAC). Examples of such systems include direct digital synthesis (DDS) products, TDMA/CDMA wireless communication systems, as well as audio and video devices.
CMOS continues to be the dominant process used to fabricate integrated circuits that contain such systems-on-a-chip. Driven by the desire for further miniaturization, advances in CMOS fabrication processes continue to lead to integrated circuits with lower and lower operating voltage and power specifications. While digital circuit designs can readily be transported to a more advanced process, analog circuit designs often produce poorer results when transported, or cannot be transported at all.
Traditional circuit designs for digital-to-analog converters suffer in this respect and generally perform poorly when moved to advanced CMOS fabrication processes. Consequently, there is a need in the art for a digital-to-analog converter providing both good AC and DC performance characteristics, and occupying minimal die space, when implemented using advanced integrated circuit fabrication processes.
SUMMARY OF THE INVENTION
The invention may be employed to provide high-performance digital-to-analog conversion suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes. The digital-to-analog converter embodiment described herein includes encoder circuitry and analog conversion circuitry. The encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number each feed into a binary-to-thermometer encoder. Each binary-to-thermometer encoder turns on the number of output signals that corresponds to the value represented at its inputs. Latch elements latch the output signals of each binary-to-thermometer encoder, and present each signal and its complement as outputs to the analog conversion circuitry.
The analog conversion circuitry includes a set of current switching cells for each segment of the binary number fed to a binary-to-thermometer encoder. Each cell in a set contributes an equal amount to the analog output of the converter. Each cell is controlled by one of the output signals of the encoder circuitry latches and its complement, to contribute its total weight to one or the other of the complementary outputs of the converter.
Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source receives its input current from a master current bias circuit through a pair of mirror transistors. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.
Hierarchical gradient symmetry cancellation techniques are employed to assign switching order assignments to the cells within each set in order to reduce integral non-linearity attributable to process-related surface gradients.
These and other purposes and advantages of the present invention will become more apparent to those skilled in the art from the following detailed description in conjunction with the appended drawings.


REFERENCES:
Takahiro Miki, Yasuyuki Nakamura, Maso Nakaya, Sotoju Asai, Yoichi Akasaka, and Yasutaka Horiba, “ An 80-MHz 8-bit CMOS D/A Converter, ”IEEE J. Solid-State Circuits, vol. SC-21, pp. 983-988, Dec. 1986.
E. Sackinger and W. Guggenbuhl, “ A High-Swing, High-Impedance MOS Cascode Circuit, ”IEEE J. Solid-State Circuits, vol. 25, No. 1, pp. 289-298, Feb. 1990.
Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh, and Nobuharu Yasawa, “A 10-b 70-MS/s CMOS D/A Converter”, IEEE J. Solid-State Circuits, vol. 32, No. 9., pp. 1465-1469, Sep. 1997.
Bruce J. Tesch and Juan C. Garcia, “A Low Glicth 14-b 100 MHz D/A Converter,” IEEE J. Solid-State Circuits, vol. 32, No. 9., pp. 1465-1469, Sep. 1997.
Behzad Razavi, ‘Principles of Data Conversion System Design’, pp. vii-xiii, 79-95, IEEE Press, New Jersey, 1995.

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