CMOS D-type latch employing six transistors and four diodes

Details CMOS D-type latch employing six transistors and four diodes CMOS D-type latch employing six transistors and four diodes

1983-03-23

1985-06-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307272A, 307452, 307481, 377105, 377117, H03K 3356, H03K 19096, H03K 2322, G11C 1928

Patent

active

045216959

ABSTRACT:
A D-type latch circuit employing only six insulated-gate field-effect transistors and four diodes includes three CMOS inverters, the first and third of which are modified inverters capable of being selectively enabled or disabled depending upon the sense of the supply voltage polarity applied thereto. To accomplish this, each of the first and third inverters includes a pair of isolation diodes. Voltage supply nodes of the second inverter are connected to latch voltage supply nodes for continuously enabling the second inverter. However, the voltage supply nodes of the first and second inverters are connected to a pair of complementary clock input nodes in a manner such that, when the clock input nodes have applied thereto one set of complementary logic voltage levels for enabling the latch, the first inverter is enabled and the third inverter is disabled, and when the clock input nodes have applied thereto a complementary set of logic voltage levels for not enabling the latch, the first inverter is disabled and the third inverter is enabled. In the overall configuration, the input node of the first inverter is connected to the data input node of the overall latch, and the output node of the first inverter is connected to the complementary data output node (Q) of the overall latch, and also to the input node of the second inverter. The output node of the second inverter is connected to the latch data output node (Q) of the overall latch. Finally, the third inverter is cross-coupled with the second inverter in a latching configuration. In particular, the input of the third inverter is connected to the output of the second inverter, and the input of the second inverter is connected to the output of the third inverter.

REFERENCES:
patent: 3716723 (1973-02-01), Heuner et al.
patent: 3716724 (1973-02-01), Parrish et al.
patent: 3808462 (1974-04-01), Parrish et al.
patent: 3887822 (1975-06-01), Suzuki
patent: 4114049 (1978-09-01), Suzuki
patent: 4275316 (1981-06-01), Knapp
patent: 4484087 (1984-11-01), Mazin et al.
RCA Datasheet, CD4042A Type "COS/MOS Quad Clocked `D` Latch".
RCA Datasheet, CD4013A Type "Dual `D`-Type Flip-Flop".
RCA Datasheet, CD4015A Type "COS/MOS Dual 4-Stage Static Shift Register".
CD4006A Type and CD4006B Type "COS/MOS 18-Stage Static Shift Register".

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