CMOS D-type flip-flop circuits

Details CMOS D-type flip-flop circuits CMOS D-type flip-flop circuits

1985-03-29

1987-09-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307243, 307452, 307481, 307269, 307272A, 377 80, H03K 326, H03K 1716, H03K 19096, H03K 3284

Patent

active

046911227

ABSTRACT:
A CMOS D-type flip-flop circuit stage for avoiding the possibilty of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.

REFERENCES:
patent: 4356411 (1982-10-01), Suzuki et al.
patent: 4409671 (1983-10-01), Daniels et al.
patent: 4484087 (1984-11-01), Mazin et al.
patent: 4551634 (1985-11-01), Takahashi et al.
patent: 4598214 (1986-07-01), Sexton
I.B.M. Tech. Dis. Bul., "Non-Overlapping Clocks for Master-Slave Latch", Hatchett.

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