CMOS current controlled delay element using cascoded complementa

Details CMOS current controlled delay element using cascoded complementa CMOS current controlled delay element using cascoded complementa

1996-07-01

1998-07-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting input current or voltage to output frequency

327100, 327309, 327285, 327287, 327288, 331 57, H03B 502, H03K 513

Patent

active

057839530

ABSTRACT:
A cascoded cmos differential delay element is described. The delay element provides a controlled delay useful in forming voltage controlled oscillators or other circuits. The delay element provides high gain enabling it to be useful in multistage delay element circuits. The circuit described includes cascoded complementary differential amplifiers and replicated bias clamps.

REFERENCES:
patent: 5300898 (1994-04-01), Chen et al.
patent: 5446412 (1995-08-01), Kimyacioglu et al.
Gray and Meyer, Analysis and Design of Analog Integrated Circuits, Chapter 10, pp. 681-713.
Maneatis, J.G., "Low-Jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques," Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, Paper No. FA8.1, pp. 130-131.
von Kaenel, V., et al., "A 320MHz 1.5mW at 1.35V CMOS PLL for Microprocessor Clock Generation," Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, Paper No. FA8.2, pp. 132-133.
Zhang, Zhong-Xuan, et al., "a 360MHz 3v CMOS PLL with 1V Peak-to-Peak Power Supply Noise Tolerance," Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, Paper No. Fa8.3, pp. 134-135.

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