CMOS contacting structure having degeneratively doped regions fo

Details CMOS contacting structure having degeneratively doped regions fo CMOS contacting structure having degeneratively doped regions fo

1986-02-18

1986-11-11

Larkins, William D.

357 12, 357 41, 357 86, H01L 2978, H01L 2988

Patent

active

046225730

ABSTRACT:
A contact structure suitable for use in a CMOS device to prevent or suppress the latch-up phenomenon in the device. It uses two degeneratively doped regions of different conductivity type with a tunnel injecting interface therebetween and a conductive segment contiguous to one of the two regions. Using such a structure as the source of an FET in a CMOS arrangement causes the emitter area and the base spreading resistance of the corresponding parasitic bipolar transistor to be reduced. This in turn causes the current gain of the parasitic transistor to decrease and the latch-up phenomenon to be prevented or suppressed.

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