CMOS constant current reference circuit

Details CMOS constant current reference circuit CMOS constant current reference circuit

2000-11-28

2002-09-10

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06448844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a CMOS constant current reference circuit suitable for use with a Rambus DRAM. More specifically, the invention relates to a CMOS constant current reference circuit capable of providing a constant current to a load, regardless of a variation in supply voltage and a variation in temperature.
2. Description of the Related Art
FIG. 1
(Prior Art) is a conventional constant current reference circuit using a CMOS transistor and a bipolar transistor. The conventional constant current reference circuit includes a negative current generating unit
10
for generating a first current I
1
having a negative (−) coefficient, a first positive current generating unit
20
for generating a second current I
2
having a positive (+) coefficient, a second positive current generating unit
30
for generating a third current I
3
having a positive (+) coefficient, and a current summing circuit
40
for summing together the first current I
1
, having a negative (−) coefficient and the second current I
2
having a positive (+) coefficient, thereby generating a constant bias current I
bias
.
The negative current generating unit
10
includes a PMOS transistor MP
3
adapted to transmit a supply voltage V
DD
to a node Nd
1
in response to a signal from the node Nd
1
, and an NMOS transistor MN
3
adapted to supply the signal from the node Nd
1
to a resistor R
1
coupled to a ground voltage Vss in response to a signal from a node Nd
3
.
The first positive current generating unit
20
includes a PMOS transistor MP
2
adapted to supply the supply voltage V
DD
to a node Nd
2
in response to a signal from the node Nd
2
. The first positive current generating unit
20
also includes an NMOS transistor MN
2
, a resistor R
2
, and a PNP type bipolar transistor Q
1
connected in series between the node Nd
2
and the ground voltage Vss. The NMOS transistor MN
2
serves to supply the signal from the node Nd
2
to the resistor R
2
in response to the signal from the Nd
3
. The PNP type bipolar transistor Q
1
is coupled at the base thereof to the ground voltage Vss, so that it is always in an ON state thereof.
The second positive current generating unit
30
includes a PMOS transistor MP
1
adapted to supply the supply voltage V
DD
to the node Nd
3
in response to the signal from the node Nd
2
. The second positive current generating unit
30
also includes an NMOS transistor MN
1
and a PNP type bipolar transistor Q
2
connected in series between the node Nd
3
and the ground voltage Vss. The NMOS transistor MN
1
serves to supply the signal from the Nd
3
to the emitter of the PNP type bipolar transistor Q
2
in response to the signal from the node Nd
3
. The PNP type bipolar transistor Q
2
is coupled at the base thereof to the ground voltage Vss, so that it is always in an ON state.
The current summing circuit unit
40
includes a PMOS transistor MP
4
adapted to supply the supply voltage V
DD
to a node Nd
4
in response to the signal from the node Nd
1
, a PMOS transistor MP
5
adapted to supply the supply voltage V
DD
to the node Nd
4
in response to the signal from the node Nd
2
, and an NMOS transistor MN
4
adapted to discharge a voltage from the node Nd
4
in response to a bias current I
bias
applied to the node Nd
4
. The bias current I
bias
flowing through the node Nd
4
has a constant value corresponding to the sum of a current I
1
, having a negative (−) coefficient, supplied through the PMOS transistor MP
4
and a current I
2
, having a positive (+) coefficient, supplied through the PMOS transistor MP
5
.
Now, the operation of the conventional constant current reference circuit having the above mentioned configuration will be described. For the current I
2
flowing through the resistor R
2
in a loop including the PNP type bipolar transistor Q
1
, resistor R
2
, NMOS transistors MN
2
and MN
1
, and PNP type bipolar transistor Q
2
, the following equations apply:
V
BE2
=I
2
×R
2
+V
BE1
I
2
=(
V
BE2
−V
BE1
)/
R
2
Hence,
V
BE2
=(
kT/q
)ln(
I
2
/I
3
),
V
BE1
=(
kT/q
)ln(
I
1
/I
3
)
I
2
=(
kT/qR
2
)ln(
I
2
/I
1
)
In the above equations, “V
BE2
” represents a voltage applied across the PNP type bipolar transistor Q
2
between the emitter and base thereof, and “kT/q” represents a thermal voltage V
T
depending on a temperature coefficient TC (V
T
=kT/q), where “k” is Boltzmann's constant, “T” is the absolute temperature in Kelvin and “q” is the magnitude of the electronic charge.
Accordingly, the current source of the current I
2
, which has a positive (+) coefficient, can be derived, based on a temperature. The current I
2
is mirrored to the PMOS transistor MP
5
by the PMOS transistor MP
2
. For the current I
1
flowing through the resistor R
1
in a loop including the NMOS transistors MN
3
and MN
1
, and PNP type bipolar transistor Q
2
, the following equations apply:
V
BE2
=I
1
×R
1
I
1
=V
BE2
/R
1
I
1
=(
kT/qR
1
)ln(
I
2
/I
3
)
Accordingly, the current source of the current I
1
, which has a negative (−) coefficient, can be derived, based on a temperature. The current I
1
is mirrored to the PMOS transistor MP
4
by the PMOS transistor MP
3
.
The current summing circuit, which consists of the PMOS transistors MP
4
and MP
5
, and the NMOS transistor MN
4
, generates a constant bias current I
bias
by summing together the mirrored current I
1
having a negative (−) coefficient and the mirrored current I
2
having a positive (+) coefficient.
This bias current I
bias
can be expressed as follows:
I
bias
=I
1
+I
2
=(
V
BE2
/R
1
)+(&Dgr;
V
BE
/R
2
)
&Dgr;
V
BE
=V
BE2
−V
BE1
However, the above mentioned conventional constant current reference circuit, which uses the bipolar transistors Q
1
and Q
2
respectively adapted to generate currents having positive (+) and negative (−) coefficients depending on an increase in temperature, has a problem in that when a negative (−) current source is formed depending on an increase in temperature, by use of the bipolar transistors Q
1
and Q
2
, it is necessary to extract model parameters by individually forming respective patterns of the bipolar transistors Q
1
and Q
2
in the manufacture of MOS transistors. Furthermore, the integration of the constant current reference circuit into a chip is uneconomical because the constant current reference circuit occupies a chip area considerably larger than that of the MOS transistors. Where the constant current reference circuit is used to generate a voltage reference, an increased variation in voltage is exhibited due to an increased variation in current resulting from a high temperature coefficient. For this reason, there is a problem in that a degradation in output occurs in the case of a system requiring a precise output.
The conventional constant current reference circuit has a problem in that it requires a number of transistors because it should have not only the circuits for generating the negative (−) current I
1
and the positive (+) current I
2
, respectively, but also the circuit for generating the constant bias current based on the sum of the currents I
1
and I
2
having respective positive (+) and negative (−) coefficients.
SUMMARY OF THE INVENTION
According to one aspect of the invention, there is provided a CMOS constant current reference circuit having a simple circuit configuration, wherein the only transistors are CMOS transistors. There are no bipolar transistors. The circuit configuration is capable of providing a constant current to a load, regardless of a variation in supply voltage and a variation in temperature.
A constant current generating means generates a constant bias current regardless of a variation of a supply voltage. A self compensation means controls the bias current generating means to maintain the bias current generated therefrom at a constant level regardl

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