CMOS compatible band gap reference

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C323S314000

Reexamination Certificate

active

06657480

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to band gap reference circuits, and more particularly, to band gap reference circuits that maintain a constant output voltage over a range of temperature and bias current.
A band gap reference circuit provides a constant output reference voltage V
REF
. Problems may arise if the output reference voltage V
REF
varies even by a small amount such as a few hundred millivolts over a range of temperature or bias current. Therefore, it is desirable to provide a band gap reference circuit that provides an output reference voltage V
REF
that is substantially constant over a range of temperature and bias current.
Previously known standard CMOS band gap reference circuits typically include an amplifier that comprises a differential pair of p-channel MOS transistors. V
REF
is determined by the voltage at the gate of one of the p-channel MOS transistors. Excess charge carriers can become trapped in the silicon to silicon dioxide (SiO
2
) interface in MOS transistors. The excess charge may cause variations in the threshold voltages of the MOS transistors in the differential pair of the amplifier. For example, the threshold voltages of the two MOS transistors in the differential pair may differ by more than 5 mV. This difference introduces an offset voltage into the amplifier which appears at V
REF
of the band gap reference circuit. The offset voltage can prevent the band gap reference circuit from being adjusted with trimming resistors so that V
REF
remains constant with temperature changes.
In addition, the charge trapped in the silicon/SiO
2
interface of the differential pair MOS transistors in the band gap reference amplifier can vary over time causing V
REF
to change over time even at a constant temperature. These variations in V
REF
cause undesirable 1/f output noise. Also, the p-channel MOS transistors in the differential pair may introduce thermal noise at V
REF
due to the nature of MOS transistors, which is also undesirable.
A further disadvantage of previously known standard CMOS band gap reference circuits is that they are sensitive to relatively small changes in the supply voltage V
CC
. Small changes in V
CC
cause variations in the bias current through the band gap reference circuit, which can cause undesirable changes in V
REF
.
It would therefore be desirable to provide a less noisy band gap reference circuit in CMOS technology that provides a substantially constant output reference voltage V
REF
over a range of supply voltage and a range of temperature.
BRIEF SUMMARY OF THE INVENTION
The present invention provides CMOS low noise band gap reference circuits that output a substantially constant reference voltage V
REF
. Band gap reference circuits of the present invention have an amplifier that includes a differential pair of bipolar junction transistors. Each of the bipolar junction transistors are coupled to a first or a second plurality of bipolar junction transistors or a first and second plurality of diodes. The first and second plurality of transistors or diodes are coupled to a plurality of resistors. When the temperature of the circuit varies over a range, the change in the voltage drop across the resistors compensates for the change in the voltage drop across the transistors or the diodes so that V
REF
remains substantially constant.
A feedback circuit is coupled to the amplifier. The feedback circuit adjusts its current to compensate for variations in the supply current so that the V
REF
remains substantially constant. The band gap reference circuits of the present invention provide a output reference voltage V
REF
that is substantially constant with variations over a range of temperature and supply voltage. Band gap reference circuits of the present invention may be fabricated using standard CMOS process techniques.


REFERENCES:
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patent: 4525663 (1985-06-01), Henry
patent: 4897595 (1990-01-01), Holle
patent: 4939442 (1990-07-01), Carvajal et al.
patent: 5923208 (1999-07-01), Tasdighi et al.
patent: 5936391 (1999-08-01), Larsen et al.
patent: 6075354 (2000-06-01), Smith et al.
patent: 6121824 (2000-09-01), Opris
patent: 6133719 (2000-10-01), Maulik
patent: 6281743 (2001-08-01), Doyle
patent: 6294902 (2001-09-01), Moreland et al.
patent: 6433529 (2002-08-01), Chowdhury
Paul R. Gray et al., “Analysis and Design of Analog Integrated Circuits”, John Wiley & Sons, Inc. 1977, pp. 338-347.
Paul Horowitz et al., “The Art of Electronics”, Cambridge University Press, 1980, pp. 335-341.

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