CMOS comparator output stage and method

Details CMOS comparator output stage and method CMOS comparator output stage and method

2005-08-02

2005-08-02

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S065000, C327S067000

Reexamination Certificate

active

06924672

ABSTRACT:
A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

REFERENCES:
patent: 5801553 (1998-09-01), Danstrom
patent: 6124759 (2000-09-01), Migliavacca
patent: 6229346 (2001-05-01), Milanese et al.
patent: 6229350 (2001-05-01), Ricon-Mora
patent: 6232801 (2001-05-01), Khoury et al.

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