CMOS clocked logic decoder

Details CMOS clocked logic decoder CMOS clocked logic decoder

1992-01-29

1993-11-02

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307481, H03K 19094, H03K 19096

Patent

active

052586669

ABSTRACT:
The present semiconductor logic circuit includes a first-stage logic circuit section comprising of a first precharging transistor, a first grounding transistor, and a first logic element and a second-stage logic circuit section comprising of a second precharging transistor, a second grounding transistor, and a second logic element. The first precharging transistor has the common terminal connected to a power terminal and receives a clock signal at the input terminal. The first grounding transistor has the common terminal connected to the ground and receives a clock signal at the input terminal. The first logic element has the grounding end connected to the output terminal of the first grounding transistor and the output end connected to the output terminal of the first precharging transistor. The second precharging transistor has the common terminal connected to a power terminal and the input terminal connected to the output end of the first logic element. The second grounding transistor has the common terminal connected to the ground and the input terminal connected to the output end of the first logic element. The second logic element has the grounding end connected to the output terminal of the second grounding transistor and the output end connected to the output terminal of the second precharging transistor.

REFERENCES:
patent: 3665473 (1972-05-01), Heimbigner
patent: 3796893 (1974-03-01), Hoffman et al.
patent: 4040015 (1977-08-01), Fukuda
patent: 4827160 (1989-05-01), Okano
patent: 5015882 (1991-05-01), Houston et al.

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