CMOS clock generator having an adjustable overlap voltage

Details CMOS clock generator having an adjustable overlap voltage CMOS clock generator having an adjustable overlap voltage

1989-12-04

1991-08-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307451, 307601, 307605, 3072021, H03K 513, H03K 19094, H01H 3736

Patent

active

050417380

ABSTRACT:
A CMOS clock generator for generating internal CMOS phase clock signals having an adjustable overlap voltage includes a first circuit (18) having a first input responsive to an input clock signal for generating a first phase clock signal (01) on its output and a second circuit (22) having a first input responsive to the input clock signal for generating a second clock signal (02) on its output. The overlap voltage between the phase clock signals are adjustable either up or down to speed up or slow down a semiconductor chip after fabrication. This is achieved by the utilization of a laser to break or open up fuses connected to electrodes of transistor devices.

REFERENCES:
patent: 4277699 (1981-07-01), Brown et al.
patent: 4757217 (1988-07-01), Sawada et al.
patent: 4855617 (1989-08-01), Ovens

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