Amplifiers – With semiconductor amplifying device – Including field effect transistor
Reexamination Certificate
2002-04-12
2004-12-07
Nguyen, Khanh V. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including field effect transistor
C330S292000
Reexamination Certificate
active
06828858
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally concerns CMOS power amplifiers, particularly as are operated class AB.
The present invention particularly concerns CMOS power amplifier circuit design, particularly as operated class AB and particularly as employ an NMOS input transistor, canceling at least one circuit nonlinearity.
2. Background of the Invention
2.1 General Background of the Invention
In a wireless communications system the linearity and efficiency of the system power amplifier(s) directly limits the performance of the entire system. The efficiency of the power amplifier is critical for extending the battery lifetime, while its linearity is necessary for the transmission of a quality digital signal.
The Class AB power amplifier is widely used in wireless communications systems because it is relatively easy to design and build, and has fairly good linearity and efficiency. Most recently, circa 2001, CMOS RF power amplifiers are receiving more and more attention because these amplifiers are more cost effective than are amplifiers constructed from GaAs and silicon bipolar transistors while being suitably integrated with other CMOS IC parts, primarily digital logic. Understanding the sources of any nonlinearity in NMOS Class AB amplifier is useful for improving its performance.
The linearity of CMOS Class AB power amplifier is mostly limited by two sources. The first source is the nonlinearity of the amplifier input capacitance, which can be modeled as (1) a gate-to-drain capacitance C
gd
in electrical series with a CMOS transistor selectively conducting current I
d
, plus (2) a gate-to-source capacitance C
gs
in electrical parallel with the same CMOS transistor. (To complete the model, a drain-to-source resistance R
ds
, and a drain-to-source capacitance C
ds
are also, further, in electrical parallel with the CMOS transistor.)
When the CMOS transistor toggles on and off during Class AB operation, its gate capacitance C
gs
changes dramatically. This varying capacitance will cause a nonlinearity at the gate. In other words, the gate voltage V
gd
will be a nonlinear version of the input signal because of this capacitance.
This equivalent circuit of a CMOS transistor at the signal input of a class AB CMOS power amplifier may be simulated and analyzed, with, by way of example, SPICE, for the actual parameters of various CMOS technologies, for example the Mosis HP CMOS 0.6 pm technology. For the technology C
gs
roughly changes from 1 pF/mm to 0 pF/mm as the CMOS transistor is turned on and off.
A second source of nonlinearity is the nonlinear transconductance G
m
of the CMOS transistor. When the CMOS transistor is switching on and off, its drain current is also switching on and off, thus making the transconductance G
m
to be a nonlinear function of the transistor gate voltage V
gs
. The present invention will show how to minimize this second nonlinearity.
These non-linearities are not only of considerable percentage difference, they are noticeable in the circuit response of a high-power class AB amplifier. As requirements for driving lower and lower (speaker impedance) have arisen (i.e., 32 ohms goes to 4 ohms), while power FETs grow larger and larger, the parasitic capacitance of these FETs C
gs
continues to grow.
In view of the foregoing, a need thus exists for a FET, and particularly a CMOS FET power amplifier that manages these effects better while remaining capable and efficient of high drive capability (and, likely also, low quiescent current drain).
2.2 Specific Prior Art to the Invention
U.S. Pat. No. 4,315,223 to Haque for an OPERATIONAL AMPLIFIER WITH IMPROVED FREQUENCY COMPENSATION is of relevance to the present invention for showing that the effects of circuit capacitance may be compensated. The Haque patent concerns an operational amplifier circuit (i.e., not a class AB amplifier circuit) comprised of complementary MOS transistors with a bias section, a differential amplifier section, a level shift stage and an output stage. The circuit provides for frequency compensation using two capacitors. One capacitor, connected between the differential amplifier section and the output stage through a CMOS transmission gate that functions as a resistor, acts as the dominant pole of the transfer function. A second capacitor between the amplifier section output node and a level shift transistor, functions to remove the secondary poles in the transfer function and cause the dominant pole to occur at a higher frequency.
U.S. Pat. No. 4,988,902 to Dingwall for a SEMICONDUCTOR TRANSMISSION GATE WITH CAPACITANCE COMPENSATION is if relevance to the present invention for showing that a semiconductor element—herein a transfer gate—may be used to supply a capacitance that is used in a circuit (not an amplifier circuit) for purposes of capacitance compensation. The Dingwall patent shows a transmission gate employing a pair of capacitors ahead of and a pair of capacitors behind a transistor. One capacitor of each pair is supplied with a control voltage pulse that leads and the other with a control voltage pulse that lags the complement of a control voltage pulse supplied to the gate of the transistor. The capacitors are typically each a MOS transistor with the gate serving as one terminal and the drain and source shorted together and serving as the other terminal. Moreover, each of the capacitors has a capacitance equal to one half the capacitance of the gate to source and gate to drain capacitance of the transistor. This circuitry makes possible charge compensation to avoid the build up of trapped charge in the transistor. The capacitance of the pair of capacitors ahead of the transistor is approximately equal to the gate-to-drain parasitic of the transistor and the capacitance of the pair of capacitors behind the transistor is equal to the parasitic capacitance of the gate-to-source of the transistor.
U.S. Pat. No. 5,148,065 to Krenik for CURRENT STEERING CIRCUITS AND METHODS WITH REDUCED CAPACITIVE EFFECTS concerns capacitance compensation techniques used to reduce capacitive effects that impact on the performance of certain current steering circuits. The circuits dealt with by Krenik—switching circuits—are not equivalent to the class AB amplifier circuit of the present invention. The techniques of Krenik in modifying the physical layout and structure of components, mainly transistors, used to implement a current steering circuit, are different than the compensation/cancellation technique of the present invention will be seen to be. Nonetheless, Krenik shows how capacitive effects arise in semiconductor, including CMOS, circuitry, and the limitations of semiconductor technology in compensation for these capacitive effects.
In one isolation technique of Krenik a resistor (R) or a diode (D) is coupled to a data-switched transistor to dampen voltage perturbations associated with the gate-to-source capacitance. In another technique a transistor (PDV) is included in either the output or ground legs of the current steering circuit to provide a design variable to counteract the capacitive effects of the associated data-switched (PDX/NDX) or voltage-controlled (PREF) transistor. In a bipolar substitution technique a data-switched bipolar transistor (QDX) is substituted for the data-switched MOS transistor, and made sufficiently small to significantly reduce junction capacitance. In addition, capacitive effects can be reduced by introducing fabrication alterations such as fabrication layouts in which the transistor's source contact is made within a U-shaped gate, and in which the transistor's moat perimeter is contoured for minimal gate area consistent with standard gate/contact spacing requirements.
U.S. Pat. No. 5,635,873 to Thrower, et al., for an OPERATIONAL AMPLIFIER HAVING DUMMY ISOLATION STAGE is of remote relevance to the present invention for showing that, rather than dealing with parasitic capacitance of a circuit, an attempt can be made—at least in a bipolar transistor circuit—to deal with circuit mismatch—presuming as
Larson Larry
Wang Chengzhou
Greer Burns & Crain Ltd
Nguyen Khanh V.
The Regents of the University of California
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