CMOS clamp circuits

Details CMOS clamp circuits CMOS clamp circuits

1990-02-15

1991-06-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307548, 307362, 3072723, 307568, 307475, H03K 19017, H03K 19092, H03K 19094, H03K 1704

Patent

active

050270087

ABSTRACT:
A CMOS clamp circuit includes a sense inverter (I5) having an input node for receiving a sense current signal and an output node for generating a voltage output, an N-channel MOS clamping transistor (N5), and a P-channel MOS clamping transistor (P5). The N-channel clamping transistor (N5) has its drain connected to an upper power supply potential (VCC) and its source connected to the input node of the inverter (I5). The P-channel clamping transistor (P5) has its drain connected to a lower power supply potential (VSS) and its source connected to the input node of the sense inverter (I5). The gates of the N-channel and P-channel transistors (N5, P5) are connected to the output node of the sense inverter (I5). An enabling transistor and a power-down transistor may also be provided so as to operate the clamp circuit in a power-down mode of operation.

REFERENCES:
patent: 3728556 (1973-04-01), Arnell
patent: 4140930 (1979-02-01), Tanaka
patent: 4216390 (1980-08-01), Stewart
patent: 4490633 (1984-12-01), Noufer et al.

Affiliated with

Also associated with

Rating

CMOS clamp circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS clamp circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS clamp circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1042271