CMOS Circuit with reduced power dissipation and a digital data p

Details CMOS Circuit with reduced power dissipation and a digital data p CMOS Circuit with reduced power dissipation and a digital data p

1982-10-29

1986-02-11

Thomas, James D.

Boots, shoes, and leggings

364707, G06F 104, G06F 922

Patent

active

045702195

ABSTRACT:
In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first inverter and which is also constructed of CMOS field effect transistors, the supply of clock signals to the first inverter is stopped in response to a particular microinstruction. After the supply of clock signals is stopped, the output voltage of the first inverter is clamped to a predetermined value, thus reducing the power dissipation in the dynamic CMOS circuit and also preventing the deterioration of data during the stopping of clock signals.Y

REFERENCES:
patent: 4134073 (1979-01-01), MacGregor
patent: 4137563 (1979-01-01), Tsunoda
patent: 4164666 (1979-08-01), Hirasawa
patent: 4218876 (1980-08-01), Hashimoto
patent: 4241418 (1980-12-01), Stanley
patent: 4267577 (1981-05-01), Hashimoto
patent: 4316247 (1982-02-01), Iwamoto
patent: 4434465 (1984-02-01), McDonough

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