Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-07-21
2002-06-11
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S351000, C257S357000, C257S383000, C257S374000, C257S522000, C257S523000
Reexamination Certificate
active
06404034
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention pertains to integrated circuits and, more particularly, to a CMOS circuit with all-around dielectrically insulated source-drain regions.
Circuits of that kind with all-around insulation of source-drain regions have the advantage that very small distances between n and p channels can be realized, in which parasitic pn junctions are largely prevented. Faster circuits can be obtained and flat source-drain doping profiles can be realized with a smaller film resistance.
Prior art circuits with all-around insulated source-drain regions can only be manufactured with substantial difficulty. Normally, so-called SOI techniques are employed (SOI=silicon on insulator), in which, for example, by using the so-called SIMOX process (separation by implantation of oxygen) or BESOI process (bonded etched-back silicon on insulator), a thin, monocrystalline silicon layer is produced on a trenched insulation layer, generally comprised of silicon dioxide. The production of the monocrystalline silicon layer, in which the channel regions of the MOS transistor are then produced, on the insulation layer is difficult, time-consuming, and costly.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a CMOS circuit with all-around insulated source-drain regions, which overcomes the above-mentioned disadvantages of the heretofore-known devices.
With the foregoing and other objects in view there is provided, in accordance with the invention, a CMOS circuit assembly, comprising:
a monocrystalline silicon body;
all-around dielectrically insulated source-drain regions formed in said silicon body;
the silicon body having trenches etched in the source-drain regions, the trenches being filled with undoped or only lightly doped silicon.
The CMOS circuit according to the invention differs from a circuit manufactured using SOI techniques primarily by the fact that the channel regions are a component of the wafer comprised of monocrystalline silicon. The insulation of the source-drain regions is based on the feature according to which trenches are produced in the source-drain regions and are filled with silicon. According to the invention, the trenches produced in an N or P channel resistor are filled with undoped or very low doped silicon. The material with these doping conditions may also be referred to as substantially undoped silicon. The silicon deposited in the trenches is therefore completely or nearly completely depleted and consequently represents a dielectrically insulating layer. The capacitance of the dielectrically insulating layer is determined essentially by its permittivity and thickness. On the other hand, the capacitance is largely independent of the voltage applied.
In principle, monocrystalline, polycrystalline, or amorphous silicon is suitable for filling the trenches in the source-drain regions. The trenches may, for example, be filled by means of conformal depositing of polycrystalline or amorphous silicon. In accordance with an additional feature of the invention, undoped silicon is used, which has been deposited in the trenches by means of selective epitaxy (so-called SEG). Trenches with a small trench diameter and a large aspect ratio are suitably filled by means of conformal depositing of polysilicon or amorphous silicon. Then, the deposited silicon is isotropically etched back to the trench surface, i.e. to the upper rim of the trench, or to slightly below the trench surface. The processes conventionally employed for etching silicon can be used here.
If in lieu of undoped silicon, very low doped silicon is used, this can in principle be doped using all of the compounds usually employed for doping silicon, for example, boron, phosphorus, or arsenic. The degree of doping is chosen so that the filled trench continues to have a sufficient insulating effect in comparison to the surrounding substrate. Accordingly, no specific numerical doping concentration need be provided here. Instead, those skilled in the art will readily know how to adjust the doping concentration so as to obtain sufficient resistivity of the silicon filler.
After the filling of the trenches etched into the source-drain regions, the silicon in the upper trench region is doped in a conventional manner. This produces the highly doped source and drain zones of the transistor. All materials normally employed for doping source-drain zones can be used. Phosphorus and arsenic are particularly suitable doping atoms for N channel transistors and primarily boron may be mentioned for P channel resistors.
In order to reduce the film resistance, a metal silicide layer can also be deposited on source and drain zones. Preferably, the metal silicide layer ends with the upper rim of the trench. The metal silicide layer may be a titanium silicide layer produced in a usual manner on the doped silicon in the upper trench region. So-called salicide processing is particularly suitable (salicide=self aligned silicide).
The size of the etched trenches that are filled with undoped or very lightly doped silicon depends on the embodiment of the respective MOS transistors to be dielectrically insulated. In a suitable embodiment, the trench cross section essentially corresponds to the area of the corresponding source or drain area in order to assure a complete insulation over this area. The depth of the trenches for conventional CMOS transistors generally lies in the range from approximately 0.3 to 1 mm and in particular between 0.5 and 0.7 mm.
With the above and other objects in view there is also provided, in accordance with the invention, a process for manufacturing a CMOS circuit assembly with all-around dielectrically insulated source-drain regions. The process comprises the following steps:
anisotropically etching trenches in source-drain regions of a monocrystalline silicon body;
filling the trenches with undoped or very lightly doped silicon;
isotropically etching the silicon down to at least a rim of the trench; and
doping the silicon in an upper trench region thereof.
In accordance with a preferred mode of the invention, these process steps are carried out after the structuring of the gate electrode and the production of the LDD (lightly doped drain) areas. The latter manufacturing steps can be carried out in the conventional manner.
Following the last of the above-noted four steps, a metal silicide layer may be produced in the source-drain regions, which adjoins the doped silicon in the upper trench region.
In accordance with again an additional feature of the invention, first the trench insulation is carried out for the lateral insulation of the individual transistors of the CMOS circuit. Known processes can be employed here, such as so-called shallow trench insulation, which uses silicon dioxide, for example, as the insulation material. After conventional formation of the gate oxide and the production of the gate electrode by depositing and structuring polysilicon in a conventional process, the flanks of the gate electrode are insulated in a conventional manner (manufacturing of the spacer). Then, the source and drain zones of the LDD transistors are produced by ion implantation by means of known process steps. This is followed by the above described four steps and, if desired, the depositing of a metal silicide layer onto the doped silicon in the trenches.
In the filling of the etched trenches with silicon (the filling step), attention must be paid that the process temperature is chosen so that in the already doped regions of the substrate, no diffusion of the doping atoms is triggered. The upper region of the silicon filler (the doping step) is doped at low energy and with short-term tempering at a low temperature.
The remaining process steps for manufacturing the finished CMOS circuit are then carried out in a manner which is known to those of skill in the art.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as emb
Kerber Martin
Widmann Dietrich
Abraham Fetsum
Infineon - Technologies AG
Mayback Gregory L.
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