CMOS Circuit overvoltage protection

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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361 18, 361 91, H02H 904

Patent

active

045730997

ABSTRACT:
A CMOS circuit (10) for preventing overvoltage between two supply nodes (12,14) makes use of vertical NPN bipolar transistors (80,84) for their current-carrying capability. Zener diodes (16,18,20,22) and a resistor (24) generate a sensing voltage which is amplified by a vertical bipolar transistor (28) and coupled to one input of a comparator (40) which has the other input at a bias voltage node (52) of a voltage divider (54,56,58,60). The comparator output (50) is coupled to the input of a transimpedance transistor (72) which drives the input current of a current mirror (66,74). The output (78) of the current mirror turns on the current-carrying transistors (80,84). Positive feedback for latching is provided by connecting the common gates of the current mirror transistors to the gate of a feedback transistor (86) which has its current path connected between the one supply node and the base (26) of the first bipolar transistor. The vertical bipolar transistors (28,80,84) of the circuit include guard rings (37) of heavily doped material about the emitter (32) and base (34) regions at the surface and tied to the collector voltage.

REFERENCES:
patent: 3395290 (1965-10-01), Farina
patent: 3558979 (1971-01-01), Lorenz
patent: 3594612 (1971-07-01), Gately
patent: 3793535 (1974-02-01), Chowdhurl
patent: 3823353 (1974-07-01), Berger et al.
patent: 3934175 (1976-01-01), Clark
patent: 4445160 (1984-04-01), Gordon

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