CMOS circuit for receiving ECL signals

Details CMOS circuit for receiving ECL signals CMOS circuit for receiving ECL signals

1992-07-06

1994-02-01

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 3072968, H03K 190175

Patent

active

052834824

ABSTRACT:
A CMOS circuit for receiving ECL signals includes a triple-feedback arrangement for dynamically biasing a current source transistor of a differential amplifier of the CMOS circuit. The CMOS receiver circuit of the present application comprises a differential amplifier for generating an output signal representative of the difference between a reference signal and an ECL input signal and an inverter circuit for receiving the output signal and generating a CMOS compatible output signal. The differential amplifier includes a first current source transistor. A first CMOS transistor is connected to receive the ECL input signal and a second CMOS transistor is connected to receive the reference signal. The first and second CMOS transistors have their drains coupled to first and second load transistors, respectively, and their sources coupled to one another and to a second current source transistor for generating a first control signal representative of the difference between the ECL input signal and the reference signal at the drain of the first CMOS transistor. A first feedback path connects the first control signal to the second current source transistor. A second feedback path connects the first control signal to the first and second load transistors. A third feedback path connects the drain of the second CMOS transistor to the first current source transistor for dynamically biasing the first current source transistor.

REFERENCES:
patent: 4716307 (1987-12-01), Aoyama
patent: 4841175 (1989-06-01), De Man
patent: 4972517 (1990-11-01), Kondou
patent: 5157285 (1992-10-01), Allen

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