CMOS circuit for averaging digital-to-analog converters

Details CMOS circuit for averaging digital-to-analog converters CMOS circuit for averaging digital-to-analog converters

1991-05-28

1992-09-08

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

341136, H03M 182

Patent

active

051462257

ABSTRACT:
A CMOS circuit for averaging digital-to-analog converters includes a shift register of series-connected master and slave cells controlled by a shift clock. The input of the shift register is supplied with a pulse-density-modulated data signal, and the outputs of each of the master and slave cells are connected to a data-dependent control input of a multistage gate circuit. The gate circuits are controlled by a gate clock and cause constant currents to be switched via two buses to the input and output of a p-channel current mirror in accordance with the state of the master or slave cell. The input of a current mirror is constantly supplied with one-half the sum current of the constant-current sources, and the current mirror provides current scaling, preferably by a factor of 0.5.

REFERENCES:
patent: 4725813 (1988-02-01), Miyada
patent: 4800365 (1989-01-01), White et al.
patent: 4947171 (1990-08-01), Pfeifer et al.

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