CMOS cell for logic operations with fast carry

Details CMOS cell for logic operations with fast carry CMOS cell for logic operations with fast carry

1988-04-27

1990-02-27

Clark, David L.

Boots, shoes, and leggings

364758, G06F 750, G06F 752

Patent

active

049051792

ABSTRACT:
The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the second consists of a 4-transistor series cirucit, two P-MOS (T3, T4) and two N-MOS (T5, T6) geenrating carry output CoutN complemented when the two operands have equal logic levels.

REFERENCES:
patent: 4601007 (1986-07-01), Uya et al.
patent: 4621338 (1986-11-01), Uhlenhoff
patent: 4685079 (1987-08-01), Armer
patent: 4706210 (1987-11-01), Snelling et al.
patent: 4739503 (1988-04-01), Armer et al.
patent: 4768161 (1988-08-01), Bechade et al.
patent: 4817030 (1989-03-01), Lee et al.
Oberman, R. M. M, Digital Circuits for Binary Arithmetic, pp. 46-52, 1979, Halsted Press, New York.

Affiliated with

Also associated with

Rating

CMOS cell for logic operations with fast carry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS cell for logic operations with fast carry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS cell for logic operations with fast carry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-178673