CMOS Cell array with transistor isolation

Details CMOS Cell array with transistor isolation CMOS Cell array with transistor isolation

1984-04-16

1986-02-11

Edlow, Martin H.

357 45, H01L 2702

Patent

active

045701768

ABSTRACT:
A new technique for forming CMOS custom logic circuits is disclosed wherein standard cells (10,12,14) are used and the prior art technique of field oxide isolation (16) is replaced with transistor isolation (68-71). That is, the boundaries (18,20,22,24) between the cells are formed by transistors that are permanently "off", i.e., tied to the positive or negative voltage supply, depending on whether the transistors are p-channel or n-channel devices, respectively. Therefore, instead of having to deposit separate p+ and n+ source/drain diffusions for each cell, as in the prior art, a single p+ diffusion strip (60) and a single n+ diffusion strip (62) are utilized, where the polysilicon mask of both the logic and isolation transistors defines the cell sizes. Thus, the p+ and n+ diffusions become generic steps which do not vary from circuit to circuit, decreasing the turnaround time associated with custom logic circuit layout and design.

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