CMOS buffer with complementary outputs having reduced...

Details CMOS buffer with complementary outputs having reduced... CMOS buffer with complementary outputs having reduced...

2006-07-31

2008-10-07

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S083000

Reexamination Certificate

active

07432746

ABSTRACT:
A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels includes first and second branches outputting first and second complementary output signals, respectively. Each branch includes a PMOS and an NMOS transistor connected in series with a voltage-swing adjusting transistor between a first supply voltage and a second supply voltage. Control terminals of the PMOS and NMOS transistors each receive one of the complementary input signals, and a control terminal of the first voltage-swing adjusting transistor receives a first bias voltage. When the complementary input signal has a first voltage level, the voltage-swing adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the voltage-swing adjusting transistor is shut-off. No current flows in either branch when the buffer is in a static state.

REFERENCES:
patent: 6249145 (2001-06-01), Tanaka et al.
patent: 6806734 (2004-10-01), Cairns et al.
patent: 6897696 (2005-05-01), Chang

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