CMOS buffer circuit which is not influenced by bounce noise

Details CMOS buffer circuit which is not influenced by bounce noise CMOS buffer circuit which is not influenced by bounce noise

1991-01-16

1993-01-12

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307263, H03K 1716

Patent

active

051792982

ABSTRACT:
This invention relates to an input buffer circuit including a NOT circuit composed of N-channel MOS transistor (NMOST) and P-channel MOS transistor (PMOST). This adjusts the resistance value between the NMOST and grounding voltage VSS, or the resistance value between the PMOST and supply voltage VCC, or both resistance values so as to decrease the current flowing the supply voltage VCC to the grounding voltage VSS. According to the construction, the power consumption is suppressed, and floating of grounding voltage VSS and lowering of supply voltage VCC may be prevented, so that the switching level of the input signal will not be deviated from the target value.

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patent: 5021685 (1991-06-01), Kihara

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