CMOS buffer circuit

Details CMOS buffer circuit CMOS buffer circuit

1983-01-25

1986-03-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307579, 307585, 307290, 307270, H03K 19094, H03K 17687

Patent

active

045786003

ABSTRACT:
A CMOS logic input circuit comprises two complementary transistor pairs, TR1 and TR2; TR3 and TR4 coupled in series between the supply rails. The gates of n-channel transistor TR4 and p-channel transistor TR1 are coupled to the positive and negative supply rails respectively. A switching function is performed by TR2 and TR3.
The arrangement is such that the switching threshold is substantially independent of transistor characteristics.

REFERENCES:
patent: 3873856 (1975-03-01), Gerlach et al.
patent: 4023122 (1977-05-01), Oura
patent: 4122360 (1978-10-01), Kawagai et al.
patent: 4297596 (1981-10-01), Eckert
patent: 4459494 (1984-07-01), Takakura
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4475050 (1984-10-01), Noufer

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