CMOS binary counter

Details CMOS binary counter CMOS binary counter

1987-04-02

1988-07-19

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular transfer means

Including logic circuit

377117, 377121, H03K 2344, H03K 2117

Patent

active

047590432

ABSTRACT:
A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.

REFERENCES:
patent: 3422254 (1969-01-01), Lundin
patent: 3798554 (1974-03-01), Sadlak
patent: 3870962 (1975-03-01), D'Errico
patent: 3943378 (1976-03-01), Beutler
patent: 4037085 (1977-07-01), Minorikawa
patent: 4214173 (1980-07-01), Popper
patent: 4297591 (1981-10-01), Roesler et al.
patent: 4611337 (1986-09-01), Evans

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