CMOS bias voltage generating circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307296R, 323286, 323311, G05F 156

Patent

active

046381848

ABSTRACT:
A bias generating circuit for reducing an external DC power supply voltage to a predetermined, lower, stable DC voltage used as a power source for internal logic circuits in a semiconductor IC chip includes an oscillator for converting the external DC voltage into a pulse signal, a smoothing circuit for converting a pulse signal into the lower DC voltage, and a control circuit interposed between the oscillator and the smoothing circuit for varying the pulse duration of the pulse signal from the oscillator to a changed pulse signal, and for regulating the lower DC voltage to a predetermined amplitude in response to the voltage variation in the lower DC voltage. The control circuit comprises a CMOS inverter, a CMOS buffer circuit for varying the pulse duration of the output signal of the CMOS inverter, and a voltage compensating circuit for controlling the transconductance of the CMOS inverter in response to the variation of the lower DC voltage.

REFERENCES:
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4300061 (1981-11-01), Mihalich et al.
patent: 4344121 (1982-08-01), Weber
patent: 4355277 (1982-10-01), Davis et al.
patent: 4420700 (1983-12-01), Fay et al.
patent: 4430582 (1984-02-01), Bose et al.

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