CMOS basic cell and method for fabricating semiconductor...

Details CMOS basic cell and method for fabricating semiconductor... CMOS basic cell and method for fabricating semiconductor...

2001-08-07

2004-10-05

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S207000, C257S208000, C257S211000, C257S365000, C257S366000, C257S773000, C257S774000

Reexamination Certificate

active

06800883

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a CMOS basic cell and a method for fabricating a gate array semiconductor integrated circuit using the basic cell.
Recently, semiconductor integrated circuits are more and more highly developed in their integration and performance in accordance with refinement of processes, and the cost and period required for the development are steadily increasing accordingly. Under such circumstances, gate arrays, which can be designed by merely modifying interconnect patterns with CAD (computer-aided design) or the like, are widely used as a method for fabricating semiconductor integrated circuits suitable for reducing the cost and period required for the development or for few-of-a-kind production.
In general, a gate array is fabricated as follows: A basic cell having a previously determined layout pattern and an interconnect pattern of a logic cell using one or more basic cells are prepared, the basic cells are automatically placed and automatically connected to each other with interconnects by using the CAD or the like.
FIG. 30
shows the structure of a conventional CMOS basic cell composed of four transistors. In
FIG. 30
, a reference numeral
1
denotes a CMOS basic cell. In the basic cell
1
, a first P-channel transistor TP
1
includes a gate electrode
2
A placed in a U shape in a plane view and dopant diffusion layers
3
A and
4
A provided on both sides of the gate electrode
2
A. The dopant diffusion layers
3
A and
4
A work as the source and the drain. A second P-channel transistor TP
2
includes a gate electrode
5
A placed in a U shape facing a reverse direction to the gate electrode
2
A of the transistor TP
1
, a dopant diffusion layer
6
A provided on one side of the gate electrode
5
A, and the dopant diffusion layer
4
A shared with the transistor TP
1
. A first N-channel transistor TN
1
includes a gate electrode
2
B placed in a U shape in a plane view and dopant diffusion layers
3
B and
4
B provided on the both sides of the gate electrode
2
B. The dopant diffusion layers
3
B and
4
B work as the source and the drain. A second N-channel transistor TN
2
includes a gate electrode
5
B placed in a U shape facing a reverse direction to the gate electrode
2
B of the transistor TN
1
, a dopant diffusion layer
6
B provided on one side of the gate electrode
5
B and the dopant diffusion layer
4
B shared with the transistor TN
1
. Furthermore, reference numerals
7
and
8
denote global power supply pattern and GND (ground) pattern provided in upper and lower portions in the drawing by using a first interconnect layer.
In
FIG. 30
, broken lines drawn in the basic cell
1
denote wiring grids. A wiring grid herein means a place where an interconnect pattern of a logic cell is disposed as a wiring track. The wiring grids are disposed so as to cross the gate electrodes
2
A,
2
B,
5
A and
5
B and the dopant diffusion layers
3
A,
3
B,
4
A,
4
B,
6
A and
6
B, the power supply pattern
7
and the GND pattern
8
of the basic cell
1
, and the interval thereof is determined in accordance with a placement pitch of the transistors or an interconnect pitch determined based on the semiconductor process rule.
At a stage of design of a logic cell, wiring is optionally determined to place on the wiring grids, and at a stage of design of a semiconductor integrated circuit using a plurality of logic cells, the interconnects are placed on the wiring grids by using a CAD system or the like. At these design stages, in the case where, for example, a second interconnect layer is used for wiring, the interconnect pitch of the second layer is generally set to the same pitch as that of a first layer for easing connection to interconnects of the first layer. The interconnect pitch is similarly determined also in the case where a third or upper interconnect layer is used for wiring. In
FIG. 30
, the number of wiring tracks of the basic cell
1
extending in the X-direction is 11 and the number of wiring tracks extending in the Y-direction is 3.
The conventional basic cell, however, has the following problem: For example, when a circuit example of a DFF (D flip-flop) shown in
FIG. 2A
is constructed by using the basic cell of
FIG. 30
, if interconnects of the first and second layers are used for the interconnects of the logic cell, a layout structure of
FIG. 31A
or
FIG. 31B
is obtained. The number of interconnect layers used in this case are three in total, that is, the first and second interconnect layers and a layer of vias for connecting the first interconnect layer to the second interconnect layer.
Alternatively, when the interconnects of the second layer alone are used for the interconnects of the logic cell with the interconnects of the first layer used as fixed interconnects as disclosed in, for example, Japanese Laid-open Patent Publication No. 1-270329, a layout structure of
FIG. 32
is obtained. The number of interconnect layers used in this case is also three in total, that is, the interconnects of the second layer and the interconnects of the upper third layer, which are necessary because the interconnects are crowded, and a layer of vias for connecting the second interconnect layer to the third interconnect layer.
Vias for connecting a gate electrode and a dopant diffusion region to the interconnects of the first layer are naturally necessary not only in the basic cell of FIG.
30
and the exemplified circuit configurations shown in
FIGS. 31A and 31B
but also every example described below. However, the vias are not directly concerned with the essence of the invention and hence are herein neither described nor shown in drawings.
FIG. 2B
is a symbol diagram of the DFF of
FIG. 2A
, and
FIG. 2C
is an operation timing chart. In
FIG. 2B
, a reference numeral
100
denotes a DATA input terminal, a reference numeral
110
denotes a CLK input terminal, a reference numeral
120
denotes an inverted CLK input terminal, a reference numeral
200
denotes a DATA output terminal, and a reference numeral
210
denotes an inverted DATA output terminal.
Layout structures of other logic cells obtained by using the conventional basic cell are as follows:
FIG. 33
shows a layout structure of a buffer circuit example of
FIG. 4A
constructed by using the basic cell of
FIG. 30
with interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of
FIG. 34
is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
FIG. 35
shows a layout structure of an ORNAND circuit of
FIG. 6A
constructed by using the basic cell of
FIG. 30
with the interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of
FIG. 36
is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
FIG. 37
shows a layout structure of a selector circuit of
FIG. 8A
constructed by using the basic cell of
FIG. 30
with the interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of
FIG. 38
is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
FIG. 39
shows a layout structure of an SRAM circuit of
FIG. 25A
constructed by using the basic cell of
FIG. 30
with the interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of
FIG. 40
is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
As described above, two interconnect layers are necessary for interconnects for a logic circuit in forming, by usi

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