CMOS-based pseudo ECL output buffer

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307455, 307475, 307354, 307242, H03K 19094, H03K 190175

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active

050897233

ABSTRACT:
The present invention provides a CMOS output buffer with ECL output characteristics that allows the outputs to be terminated in any manner desired and which is not limited by the op amp settling time. The buffer establishes a bus internally for the VOH and VOL levels and then switches between the buses using transmission gates. In the disclosed embodiment of the invention, the op amp's feedback path includes a P-channel device which is either identical to or, to conserve power, a carefully scaled down equivalent of the P-channel output device.

REFERENCES:
patent: 4841175 (1989-06-01), De Man et al.
patent: 4945258 (1990-07-01), Picard et al.
patent: 4947061 (1990-08-01), Metz et al.
Schumacher et al, "CMOS Subnanosecond True-ECL Output Buffer", IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 150-154.

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