CMOS APS with stacked avalanche multiplication layer which...

Details CMOS APS with stacked avalanche multiplication layer which... CMOS APS with stacked avalanche multiplication layer which...

2002-08-23

2004-11-23

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C257S053000, C250S370080

Reexamination Certificate

active

06821808

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to image sensors that use charge multiplying photoconversion layers to amplify the intensity of light captured by a pixel readout circuit.
BACKGROUND OF THE INVENTION
Amid the rising popularity for digital image devices such as digital cameras is a demand for increasingly higher picture resolution and for the devices to be more compact. Due to the interior space constraints in the compact housings, it is necessary to reduce the sizes of the electronic circuits in the device, including the image sensor. However, in reducing the size of the image sensor, a tradeoff exists between resolution and the signal levels outputted from the image sensor. If the resolution is kept the same upon reducing the size of the image sensor, the size of each pixel must be proportionately reduced. However, smaller pixels result in less light being collected by each pixel during image exposure, which in turn reduces the sensitivity of the image sensor. Although the reduced sensitivity effect can be offset by increasing the integration (exposure) time, this is an undesirable “solution” because increasing integration time also increases the potential for obtaining a blurred image if there is any movement by the image subject or the device during exposure. On the other hand, if the sensitivity is to be maintained without having to increase integration time upon reducing the size of the image sensor, the original pixel sizes must retained, which effectively reducing the number of pixels, and hence the resolution, in the reduced image sensor.
One solution towards achieving both a more compact size and high sensitivity is disclosed in “CMOS Image Sensor Overlaid with a HARP Photoconversion Layer,” by T. Watabe, et al., published in the Program of the 1999 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, pp. 211-214. In this image sensor, which is shown in
FIGS. 1A and 1B
, the pixel circuit
902
is overlaid with a charge multiplying photoconversion layer, such as a high-gain avalanche rushing amorphous photoconductor (“HARP”) photo-conversion layer
904
for amplifying the light signal produced by each pixel.
When a photon
906
hits the upper surface
908
of the HARP layer
904
, a charge
910
in the form of holes is generated and amplified to many times its original level while being propelled through the HARP layer
904
to the bottom side
912
. The pixel circuit
902
is electrically connected to the bottom side
912
of the HARP layer
904
such that the amplified light signal
910
, upon reaching the bottom side
912
of HARP layer
904
, is conducted into the pixel circuit
902
as electrical charge. The charge accumulates at a storage node
914
in the pixel circuit until the pixel data is read out by activating the gate of a row select switch
916
. The amount of charge accumulated at the node
914
, which is proportional to the intensity of light
906
detected, is read out. In this manner, the image sensor of
FIGS. 1A and 1B
allows each pixel to capture image data with an intensity and sensitivity equivalent to that attainable by significantly larger pixels that do not have the avalanche multiplication capability. As a result, use of a HARP layer enables the image quality to be improved without having to increase the size of the image sensor array.
In order to obtain avalanche multiplication in the HARP layer, an electric field of about 10
6
V/cm is required, which is achieved by applying an operating voltage of between 50-100 V to the HARP layer. The multiplication factor of a HARP layer is dependent on the applied operating voltage, as described in “An a-Se HARP Layer for a Solid-state Image Sensor,” by W-D. Park et al., IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, pp. 56-59, June 1999, the teachings of which are hereby incorporated by reference.
In a typical HARP image sensor, voltages of less than about 8 V are used in the pixel circuit connected beneath the HARP layer, with the pixel circuit generally having a breakdown voltage of around 20 V. When the intensity of the incident light on the image sensor is at the upper end of the detection range for the charge multiplying photoconversion layer, the voltage level accumulating at the storage diode beneath the HARP layer approaches the level of the operating voltage applied to the HARP layer. As the voltage level at the storage node rises, however, the effective voltage applied across the photoconversion layer decreases, which affects the charge amplification function of the photoconversion layer. For example, in the arrangement shown in
FIGS. 1A and 1B
, as the charge representing a detected light flows from the HARP layer
904
and accumulates on the node
914
of the storage diode, the voltage at the node
914
increases, causing the potential difference between the operating voltage V
target
applied to the HARP layer
904
and the storage node
914
to decrease. The result is pixel signal saturation and a nonlinear response in which the signal levels recorded by the imaging device are not correctly represented in the pixel output.
To address this problem, it is necessary to find a way to amplify the intensity of light signals by the same amount under bright light conditions as for lower light conditions, by either accounting for the loss of effective operating voltage across the charge multiplying photoconversion layer or otherwise addressing the decreasing amplification in bright light conditions.
BRIEF SUMMARY OF THE INVENTION
The present invention mitigates the problem of pixel saturation and nonlinear amplification of the image signal output from a charge multiplying photoconversion layer by incorporating an output control circuit into the pixel circuit connected to the charge multiplying photoconversion layer. Preferably, the output control circuit is constructed as a charge trans-impedance amplifier (CTIA) circuit including at least an operational amplifier, wherein the CTIA serves to fix the voltage level at the storage node to thereby maintain a constant effective operating potential across the charge multiplying photoconversion layer.
In a first embodiment of the invention, the output control circuit maintains the effective voltage across a photoconversion element at a constant level and provides a linear output throughout the entire operating range of the photoconversion element. A second embodiment of the invention also fixes the voltage across the photoconversion element, and further logarithmically compresses the image signal obtained from the photoconversion element. The output control circuit of the third embodiment of the invention provides a linear output signal in low light conditions until the current from the photoconversion element reaches a predetermined threshold value, whereupon the output control circuit then switches the output to a logarithmic signal in brighter light conditions. Optionally, the output control circuit of this embodiment may be constructed so that the threshold value between the linear and logarithmic output characteristics is adjustable.
These and other features and advantages of the present invention will become more apparent from the following detailed description of the invention provided below with reference to the accompanying drawings.


REFERENCES:
patent: 5818052 (1998-10-01), Elabd
patent: 2001/0045535 (2001-10-01), Yasuda
patent: 2002/0180721 (2002-12-01), Kimura et al.
Klaas Bult, “Analog Broadband Communication Circuits in Pure Digital Deep Sub-Micron CMOS,” ISSCC Dig. Tech. Papers, pp. 76-77, Feb. 1999.
Zhong-Shou Huang and Takao Ando, “A Novel Amplified Image Sensor with a-Si:H Photoconductor and MOS Transistors,” IEEE Transaction on Electron Devices, vol. 37, No. 6, Jun. 1990, pp. 1432-1438.
Isao Takayanagi et al., “Amplified MOS Imager for Soft X-ray Imaging,” IEEE Transactions on Electron Devices, vol. 42, No. 8, Aug. 1995, pp. 1425-1431.
Hon-Sum Wong, “Technology and Device Scaling Considerations for CMOS Imagers,” IEEE Transactions on Electron Devices, vol. 43, No. 12, Dec.

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