CMOS aps with stacked avalanche multiplication layer and low...

Details CMOS aps with stacked avalanche multiplication layer and low... CMOS aps with stacked avalanche multiplication layer and low...

2008-05-13

2008-05-13

Villecco, John (Department: 2622)

Television

Camera, system and detail

Solid-state image sensor

C348S217100, C348S299000, C348S301000, C348S310000, C257S438000, C250S208100

Reexamination Certificate

active

10226190

ABSTRACT:
An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components.

REFERENCES:
patent: 4973833 (1990-11-01), Takada et al.
patent: 5181092 (1993-01-01), Atsumi
patent: 5371392 (1994-12-01), Isono et al.
patent: 5557121 (1996-09-01), Kozuka et al.
patent: 5684323 (1997-11-01), Tohyama
patent: 5818052 (1998-10-01), Elabd
patent: 5892222 (1999-04-01), Elabd
patent: 6437339 (2002-08-01), Lee et al.
patent: 6741283 (2004-05-01), Merrill et al.
patent: 6936806 (2005-08-01), Kitamura et al.
patent: 2001/0045535 (2001-11-01), Yasuda
patent: 2002/0089595 (2002-07-01), Orava et al.
patent: 1187217 (2002-03-01), None
Klaas Bult, “Analog Broadband Communication Circuits in Pure Digital Deep Sub-Micron CMOS,” ISSCC Dig. Tech. Papers, pp. 76-77, Feb. 1999.
Zhong-Shou Huang and Takao Ando, “A Novel Amplified Image Sensor with a-Si:H Photoconductor and MOS Transistors,” IEEE Transaction on Electron Devices, vol. 37, No. 6, Jun. 1990, pp. 1432-1438.
Isao Takayanagi et al., “Amplified MOS Imager for Soft X-ray Imaging,” IEEE Transactions on Electron Devices, vol. 42, No. 8, Aug. 1995, pp. 1425-1431.
Hon-Sum Wong, “Technology and Device Scaling Considerations for CMOS Imagers,” IEEE Transactions on Electron Devices, vol. 43, No. 12, Dec. 1996, pp. 2131-2142.
Wug-Dong Park et al., “An a-Se HARP Layer for a Solid-state Image Sensor,” IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, Jun. 1999, pp. 56-59.
Isao Takayanagi et al., “A Stacked CMOS APS for Charge Particle Detection and its Noise Performance,” IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, Jun. 1999, pp. 159-162.
Toshihisa Watabe et al., “CMOS Image Sensor overlaid with a HARP Photoconversion Layer,” Program of 1999 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, pp. 211-214.
Yamauchi, M., et al. CMOS Image Sensor Overlaid With a Harp Photo-Conversion Film, 2000 IEEE (89-92).

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