CMOS and ECL logic circuit requiring no interface circuitry

Details CMOS and ECL logic circuit requiring no interface circuitry CMOS and ECL logic circuit requiring no interface circuitry

1991-04-02

1992-09-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307455, H03K 19092, H03K 19086

Patent

active

051480590

ABSTRACT:
An ECL circuit (12) for directly coupling to and from a CMOS circuit (10). The ECL circuit has an input node for receiving an input signal generated by a CMOS circuit. The input signal swings, or transitions, between a first potential (V.sub.0) and a second potential (V.sub.1). The ECL circuit further includes ECL core circuitry (Q.sub.3, Q.sub.4, R.sub.L), coupled to the input node and responsive the received signal, for generating an intermediate electrical signal that swings between a third potential (V.sub.2) and a fourth potential (V.sub.3) that is approximately two times (V.sub.1 -V.sub.0). The ECL circuit further includes an output driver circuit for coupling to an input of a CMOS circuit or to another ECL circuit. The output driver circuit has an input node coupled to an output of the ECL core circuitry and includes emitter followers (EF.sub.1, EF.sub.2) for generating, in response to the intermediate electrical signal swinging between V.sub.2 and V.sub.3, a first output signal tha swings between the V.sub.0 and V.sub.1.

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