CMOS and bipolar fabrication process using selective epitaxial g

Details CMOS and bipolar fabrication process using selective epitaxial g CMOS and bipolar fabrication process using selective epitaxial g

1989-03-07

1991-04-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG11, 148DIG26, 148DIG31, 156613, 437 59, 437 64, 437 90, H01L 2120

Patent

active

050100343

ABSTRACT:
A CMOS and bipolar fabrication process wherein a silicon dioxide layer initially formed over a silicon substrate is etched for forming separate collector and base/emitter regions for a bipolar device, and PMOS and NMOS regions for corresponding PMOS and NMOS devices. Buried layer implants are performed using a minimum number of masks, and then an epitaxial layer is grown over the exposed portions of the silicon substrate. The silicon dioxide walls between the devices provide full dielectric isolation between the devices, as well as between the collector and base/emitter regions of the bipolar device. Nonetheless, the oxide wall between the collector and base/emitter of the bipolar device is sufficiently small to allow the buried layer implants to joint under the wall for forming a conventional buried layer for the bipolar device. Because of the oxide walls, the minimum distance between devices may be 0.5 microns or less.

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Sze, VLSI Technology, McGraw-Hill Book Co., New York, N.Y., 1983, pp. 169-170.

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