Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1988-10-17
1991-03-12
Callahan, Timothy P.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307359, 307529, 307261, 307585, H03B 1900, G06G 700
Patent
active
049995219
DESCRIPTION:
BRIEF SUMMARY
This invention relates to a CMOS analog multiplying circuit which provides a current output whose magnitude is proportional to the product of the values of two input variables. CMOS stands for complementary metal-oxide-semiconductor structure.
Analog multiplying circuits are, of course, well known. One such circuit is described in an article entitled "A 20-V Four-Quadrant CMOS Analog Multipler" by Joseph N. Babanezhad and Gabor C. Temes found at pages 1158-1168 of IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 6, December 1985. This circuit, as do others, performs multiplication of variables which are present in the form of differential voltages and can consequently be handled by amplifiers having a differential input. Such circuits are conceived to achieve high precision multiplication of input variables whose sign can be positive or negative, i.e. they are four-quadrant multipliers. Due to their working mechanisms, the input variables have to be voltages whose DC component is of a predetermined value in order to bias correctly the differential input amplifiers. This fact and the fact that input variables have to be present in the form of differential voltages constitute a drawback in application. Also, to achieve four-quadrant multiplication with high precision, their complexity is high which results in relatively high manufacturing costs.
It is thus desirable to produce a one-quadrant multiplier which does not necessarily achieve high precision, which is of low complexity and consequently has low manufacturing costs.
Accordingly, the invention provides a CMOS analog multiplying circuit comprising a first transistor having its current electrodes coupled between a first reference voltage line and a first node and its gate electrode coupled to a first input node having, in use, an input voltage such that said first transistor operates in its triode region, a second transistor having its current electrodes coupled between said first node and an output node said output node being coupled to a second reference voltage line, and a comparator for comparing a first voltage at said first node with a second voltage at a second input node and for controlling the gate electrode of said second transistor to keep said first and second voltages substantially equal, whereby the current through said second transistor is proportional to the product of the voltages at said first input and second input nodes.
In one embodiment of the invention, the comparator comprises a differential amplifier having its inverting input coupled to said first node and its non-inverting input coupled to said second input node and whose output is coupled to the gate of said second transistor.
In a second embodiment of the invention, the comparator comprises a long-tailed pair of transistors, the node formed by their source electrodes being coupled to a constant current source, the gate of the first of the transistors forming said long-tailed pair being coupled to said second input node, the gate of the second transistor forming said long-tailed pair being coupled to said first node, the drain of said first transistor of said long-tailed pair being coupled to the input of a current mirror whose output is coupled to the drain of the second transistor of said long-tailed pair, the drain of said second transistor of said long-tailed pair constituting the output of the comparator and being coupled to the gate electrode of said second transistor.
In a preferred embodiment of the invention, said output node is coupled to the second reference line via a current mirror.
It will be appreciated that the voltages applied to the input nodes may constitute the input variables or that one or both of them may result from an appropriate conversion of current to voltage if the variables to be multiplied are currents.
The invention will now be more fully described by way of examples with reference to the drawings of which:
FIG. 1 shows a simplified version of a CMOS analog multiplying circuit according to the invention;
FIG. 2 shows a preferred embodiment
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Babanezhad, "A 20-V Four Quadrant CMOS Analog Multiplier", IEEE Solid State Circuits, vol. SC-20, No. 6, Dec. 85, pp. 1158-1168.
Bingham Michael D.
Callahan Timothy P.
Motorola Inc.
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