CMOS analog four-quadrant multiplier

Details CMOS analog four-quadrant multiplier CMOS analog four-quadrant multiplier

1989-10-11

1990-12-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307201, 328160, 364841, H03L 500, H03K 1901

Patent

active

049788736

ABSTRACT:
A four-quadrant analog multiplier circuit provides an output which is protional to two voltage inputs that each represent a multiplicand. In a first embodiment, the circuit comprises a complementary pair of field effect transistors having gain constants equal in magnitude and in which the p-channel threshold voltage is larger than the n- channel threshold voltage. The gates of the transistors are coupled in common. One input is added to a bias voltage and the voltage sum is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors, while the remaining source/drain terminals are coupled in common to provide an output node. A second embodiment of the invention is composed of two circuits as described above, where the polarities of the inputs to one pair of transistors are reversed relative to those of the second pair, and the output nodes of the individual pairs are coupled together.

REFERENCES:
patent: 4101966 (1978-07-01), Uzunoglu
patent: 4156924 (1979-05-01), Lampe et al.
patent: 4387439 (1983-06-01), Lin
patent: 4835421 (1989-05-01), Khoury et al.
patent: 4906873 (1990-03-01), Shoemaker et al.

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