CMOS analog four-quadrant multiplier

Details CMOS analog four-quadrant multiplier CMOS analog four-quadrant multiplier

1989-01-12

1990-03-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328160, 363 60, 307482, 307578, 307264, H03L 500, H03K 1901

Patent

active

049068733

ABSTRACT:
A four-quadrant analog multiplier circuit provides an output which is proportional to two voltage inputs. The circuit includes a pair of depletion mode transistors having gain constants equal in magnitude and threshold voltages equal in magnitude. The gates of the transistors are coupled in common. One input is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors.

REFERENCES:
patent: 3727078 (1973-04-01), Wollensen
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patent: 4366550 (1982-12-01), Lampe
patent: 4546275 (1985-10-01), Penna Finol et al.
patent: 4563670 (1986-01-01), Stallkamp et al.
patent: 4586155 (1986-04-01), Gilbert
patent: 4623890 (1986-11-01), Nysen
"Modeling of an Ion-Implanted Silicon-Gate Depletion-Mode IGFET", by Huang, . S. T. et al., IEEE Transactions on Electron Devices, vol. ED-22, pp. 995-1001, Nov. 1975.
"A Precise Four-Quadrant Multiplier with Subnanosecond Response", by Gilbert, B., IEEE Journal of Solid State Circuits, vol. SC-3, No. 4, pp. 365-373, Dec. 1968.

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