CMOS amplifier for memories

Details CMOS amplifier for memories CMOS amplifier for memories

1988-02-22

1990-01-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307491, 307568, 365208, H03K 1716

Patent

active

048975699

ABSTRACT:
A read amplifier for memories, using C-MOS technology, consists of a differential stage comprising an balancing circuit used, during the balancing phase, by means of a pre-charging signal and means to memorize the state of the differential stage output during the balancing phase. The invention can be applied especially to RAMs.

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patent: 4724339 (1988-02-01), Ishida
patent: 4736117 (1988-04-01), Wieser
patent: 4740760 (1988-04-01), Phan
IEEE International Solid-State Circuit Conference, vol. 28, Conf. 32, Feb. 85, pp. 64-64, 306, IEEE, Coral Gales, Fla. U.S.; K. Ochii et al., "17 ns 64K CMOX RAM With a Schmitt Trigger Sense Amplifier".
Patent Abstracts of Japan, vol. 7, No. 64 (P-183), Mar. 17, 1983, JP-A-57 208 609.
Electronic Design, vol. 33, No. 9, Apr. 1985, pp. 52-54, Hasbrouck Heights, N.J., U.S.; D. Bursky "CMOS ICs Handle High-Voltage Needs of RS-232 Interface".

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