CMOS Address buffer circuit

Details CMOS Address buffer circuit CMOS Address buffer circuit

1984-05-09

1985-12-31

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307362, 307279, 365230, H03K 19096, H03K 19017, H03K 3037, G11C 800

Patent

active

045617023

ABSTRACT:
A CMOS bistable circuit is employed as an address buffer or latch for a semiconductor memory or the like. The circuit includes a pair of differential gated inputs, one from an address terminal, and the other from a reference voltage. The same clock used to gate the inputs also preconditions the circuit to be in a balanced status, and holds off conduction of any transistor in the circuit. In this manner, a circuit of high speed, low power, and minimum complexity is provided.

REFERENCES:
patent: 4031415 (1977-06-01), Redwine et al.
patent: 4087704 (1978-05-01), Mehta et al.
patent: 4110639 (1978-08-01), Redwine
patent: 4280070 (1981-07-01), Reese et al.
patent: 4356411 (1982-10-01), Suzuki et al.
patent: 4417163 (1983-11-01), Otsuki et al.
patent: 4485317 (1984-11-01), Davies, Jr.
patent: 4496857 (1985-01-01), Chao
Lee et al., "A 80ns 5V-Only Dynamic RAM", IEEE ISSCC 79; 2 pages; Digest of Technical Papers; 2/15/79.

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