CML delay cell with linear rail-to-rail tuning range and...

Details CML delay cell with linear rail-to-rail tuning range and... CML delay cell with linear rail-to-rail tuning range and...

2008-07-22

2008-07-22

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S274000, C327S287000

Reexamination Certificate

active

11556882

ABSTRACT:
A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I0, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βpNand a second plurality of transistors having a transconductance βnN, wherein respective ratios of βnN/βpNdetermine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M0Nthat supply additional currents to the current source I0at a drain node of the third transistor.

REFERENCES:
patent: 6157266 (2000-12-01), Tsai et al.
patent: 6294962 (2001-09-01), Mar
patent: 6771105 (2004-08-01), Andrasic et al.
patent: 6943606 (2005-09-01), Dunning et al.
patent: 2004/0051573 (2004-03-01), Schrodinger

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