CMIS circuit and its driver

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 307450, 307451, H03K 19092, H03K 1716

Patent

active

052182479

ABSTRACT:
A semiconductor integrated circuit includes a complementary MIS circuit including first PMIS and NMIS transistors with their drain electrodes connected together. The integrated circuit further includes a driving level-shift which includes a second PMIS transistor having its drain electrode grounded, and having its source electrode connected to the gate of the first PMIS transistor and to a V.sub.DD voltage supply terminal via a first resistor. The level-shift circuit further includes a second NMIS transistor having its drain electrode connected directly to the V.sub.DD voltage supply terminal, having its source electrode grounded via a second resistor, and having its gate electrode connected to the gate electrode of the second PMIS transistor. An input voltage is applied to the gate electrodes of the second PMIS and NMIS transistors.

REFERENCES:
patent: 4825102 (1989-04-01), Iwasawa et al.
patent: 4959560 (1990-09-01), Ootani
patent: 5059823 (1991-10-01), Ahsanullah
patent: 5089722 (1992-02-01), Amedeo

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