Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Reexamination Certificate
2001-02-06
2004-04-20
Huynh, Ba (Department: 2173)
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
C345S215000, C700S108000, C700S159000
Reexamination Certificate
active
06724404
ABSTRACT:
FIELD
This invention relates to the field of microelectronic circuit production equipment up time determination. More particularly the invention relates to a system for determining the actual up time of a cluster tool.
BACKGROUND
For a variety of different reasons, cluster tools are increasingly used in the production of microelectronic circuits, such as semiconductor devices. A cluster tool, in its basic implementation, is typically comprised of more than one processing chamber, each of which is connected to a common transfer chamber, which in turn is connected to one or more common loading stations. Therefore, the use of cluster tools tends to increase the rate at which production pieces are processed through the processing chambers, and also tends to increase the ratio of production rate per fabrication facility size.
The pieces to be processed in the cluster tool, typically semiconductor substrates, are staged in the loading station by an operator and brought into the common transfer chamber under the programmable control of the cluster tool. The common transfer chamber is typically environmentally controlled in some manner. For example, the common transfer chamber may be kept at a reduced pressure, a low moisture content, a low oxygen content, or under the environment of a specific gas.
The substrates are processed through one or more of the different processing chambers in a selection and order determined by the cluster tool, as programmed to achieve a specific outcome. For example, one program may be set up to create a metal layer stack, with several different metal layers deposited in different ones of the processing chambers, followed by an anneal in another of the processing chambers. Other metallization systems may make use of a different set of the processing chambers in which metal layers are deposited, or use the processing chambers in a different order.
Thus, a cluster tool can be thought of as a system comprised of several discrete but often interdependent processing chambers. When the substrates have completed processing, they are typically automatically removed from the common transfer chamber and returned to the common loading station, to be taken to another processing location.
In most processing environments it is generally regarded as beneficial to be able to determine the amount of time that a particular piece of processing equipment is available for production. Because a cluster tool has several different components, it presents some rather unique challenges when determining the up time for the cluster tool. For example, because the different components tend to be interrelated, and also because the different components are typically used at different times in different orders and groupings, traditional methods of up time determination tend to be inadequate.
What is needed, therefore, is a system for determining the up time of a cluster tool.
SUMMARY
The above and other needs are met by a method for determining an up time of a multi-component tool having discrete elements, where the up time determination is based upon different processes that are to be accomplished in the multi-component tool. The discrete elements of the multi-component tool and the different processes to be accomplished in the multi-component tool are identified. Different tool states for the multi-component tool are determined by setting element states for each of the discrete elements of the multi-component tool. A first possible element state indicates that the discrete element is functional, and a second possible element state indicates that the discrete element is nonfunctional. Possible combinations of the element states of the discrete elements are identified as the different tool states of the multi-component tool.
A determination is made as to which of the different processes can be accomplished in the different tool states, and a percentage of time usage is determined for the allocation of the multi-component tool to each of the different processes. Rates associated with combinations of the different tool states with the different processes are determined. Process state efficiencies are determined from the rates and the percent of time usage allocated to the processes associated with the rates. A preliminary state efficiency for the different tool states is determined from the process state efficiencies associated with the different tool states. Percent of time conditions are determined for the different tool states, where the percent of time conditions represent ratios of time that the multi-component tool exhibits the associated tool state. The final state efficiencies for the different tool states are determined from the percent of time conditions and the preliminary state efficiencies associated with the different tool states, and the up time is determined from the final state efficiencies.
By taking into account the various states of the multi-component tool and the various factors associated with running the different processes on the multi-component tool in these various states, the method as described above provides a real world determination of the up time for a multi-component tool, such as a cluster tool. Other methods, such as serially multiplying the individual up times for each of the discrete element, or looking at the discrete elements in parallel to determine whether any process can possibly be run in the multi-component tool, tend to either under estimate or over estimate respectively the actual up time of the multi-component tool, as based upon the processes that are actually schedule to run in the multi-component tool.
REFERENCES:
patent: 5914879 (1999-06-01), Wang et al.
patent: 2002/0116083 (2002-08-01), Schulze
Hann, Jr. Thomas C.
Meyer Mark D.
Meyer Theodore O.
Huynh Ba
LSI Logic Corporation
Luedeka Neely & Graham
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