Closely-spaced double level conductors for MOS read only

Details Closely-spaced double level conductors for MOS read only Closely-spaced double level conductors for MOS read only

1978-05-18

1983-05-31

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29591, 148187, H01L 2128

Patent

active

043854320

ABSTRACT:
Closely-spaced conductors can be used in a semiconductor integrated circuit such as an MOS read only memory or ROM formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, and output and ground lines are defined by elongated N+ regions. To allow the spacing between adjacent polysilicon address lines to be closer, alternate rows employ first or second level polysilicon which can even overlap if necessary. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide.

REFERENCES:
patent: 3225261 (1965-12-01), Wolf
patent: 4097885 (1978-06-01), Walsh
patent: 4099317 (1978-07-01), Su
patent: 4143178 (1979-03-01), Harada et al.
patent: 4151020 (1979-04-01), McElroy
patent: 4347656 (1982-09-01), Smith et al.

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