Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-09-10
2001-07-17
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S105000, C327S101000, C331S00100A, C331S017000
Reexamination Certificate
active
06262609
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is within the field of voltage-to-frequency converters (V/F converters). In particular, the invention comprises a closed-loop V/F converter including a voltage-controlled oscillator (“VCO”) configured in a feedback voltage-locked loop. This V/F converter is especially useful in combination with a phase-locked loop (“PLL”) frequency synthesizer for an RF receiver of a wireless radio.
2. Description of the Related Art
A primary constraint on the design of a phase-locked loop frequency synthesizer in a wireless radio is its phase-noise performance. The phase-noise of the PLL, generally, is dominated by the phase-noise of the constituent VCO in the range of interest. The phase-noise of the VCO is inversely proportional to its power consumption. Thus, in order to meet the phase-noise requirements for the PLL, it is generally necessary to use expensive, high-quality VCO circuits, and/or it is necessary to increase the power of the VCO, which is disadvantageous in portable radio devices where power is limited.
A free-running VCO is essentially an open-loop system, where any noise in the system directly affects the output with no means of correction. When configured in a phase-locked loop, which is a closed-loop feedback system, the loop corrects the noise of the VCO within its bandwidth. Thus the VCO phase-noise is inhibited within the PLL bandwidth.
In this type of system, it is beneficial to increase the PLL bandwidth as much as possible. But, the maximum PLL bandwidth is limited by the spurious rejection of the loop. Hence, the PLL bandwidth is generally one order of magnitude less than the reference frequency. In a classical PLL-based frequency synthesizer in a wireless transceiver, the reference frequency would be equal to the channel spacing, and the loop does not inhibit the VCO phase-noise in the range of interest.
Therefore, a new architecture for a frequency synthesizer incorporating a VCO is needed.
SUMMARY OF THE INVENTION
The present invention comprises a closed-loop V/F converter that includes a VCO placed in a feedback voltage-locked loop (VLL). This converter achieves both wide bandwidth (for good phase-noise suppression) and good spurious rejection. The closed-loop V/F converter may be further configured in a larger PLL to achieve accurate channel selection that is independent of temperature and process variations.
In the V/F converter, the VCO output is first divided down to a lower frequency and then fed to a frequency-to-voltage converter (F/V). The DC value of the F/V output is proportional to the input frequency. The F/V output is then compared to a reference voltage to generate an error signal. This error signal is filtered by a loop filter and fed back to the VCO control input to create the voltage-locked loop. Although described in terms of a V/F converter, the concepts described in this application are also applicable to a current-to-frequency converter (I/F).
The present invention configures an ordinary VCO in a novel voltage-locked loop to create a V/F converter that overcomes many of the design problems with using VCOs in a radio device. Because the VCO is configured in a feedback loop, the phase noise of the VCO is corrected and inhibited within the loop bandwidth. By making the loop bandwidth sufficiently large, the VCO noise contribution to the V/F converter's output is greatly reduced. This relaxes the design constraints on the VCO, thus allowing for a VCO with lower power consumption and possibly a monolithic VCO.
The bandwidth of the loop in this V/F converter circuit is not limited by spurious rejection (as with a classical PLL), because the voltage spurs occur at the frequency at which the F/V is operating. Since this frequency can be designed to be very large (e.g., 50MHz) without affecting tunability, the spurs are not close to the carrier frequency, and are also sufficiently attenuated by the loop transfer function.
REFERENCES:
patent: 4458214 (1984-07-01), Lakomy
patent: 4847569 (1989-07-01), Dudzaik et al.
patent: 5335365 (1994-08-01), Ballantyne et al.
patent: 5521556 (1996-05-01), O'Shaughnessy et al.
patent: 5821816 (1998-10-01), Patterson
patent: 6016069 (2000-01-01), Sadowski
patent: 6078224 (2000-06-01), Ujiie
Elmasry M. I.
Hafez Amr N.
Dinh Paul
Jones Day Reavis & Pogue
Meyer, Esq. Charles B.
Pathiyal, Esq. Krishna K.
Research In Motion Limited
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