Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1998-07-02
2001-02-13
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S519000, C709S241000
Reexamination Certificate
active
06188411
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer systems, and more particularly to addressing methods for indexed registers in computer chips.
BACKGROUND OF THE INVENTION
Computer systems such as personal computers (PCs) have a variety of controller integrated circuits (ICs) or chips. These controller chips control subsystems such as for graphics, the keyboard, hard, floppy, and optical disks, and general system logic such as memory bus. Controller chips are continually being improved to increase the performance and feature sets of computer subsystems.
Controller chips are often programmable. For example, the graphics controller can be programmed with the display resolution, such as the number of pixels in a horizontal line, or the number of lines on a screen. Memory-controller chips can be programmed with numbers of clock cycles for memory accesses, so that the timing signals generated by the controller chip can be adjusted for faster memory chips or faster bus clocks.
When the computer is initialized or booted, lower-level software such as the BIOS or graphics drivers can program the controller chips by writing values into programmable registers on the controller chips. Users or higher-level programs can adjust features such as resolutions by writing different values to these registers. For example, a video game can change the resolution and color depth by writing to resolution registers in the graphics controller chip when the game program is started.
The microprocessor's address space is typically partitioned into memory and input/output (I/O) address spaces. While a large memory address space such as 4 GigaBytes (32 address bits) is provided, the I/O address space is typically much smaller, perhaps only 64 Kbytes (16 address bits). I/O addresses are used for accessing peripheral devices such as I/O ports, disk drives, modems, mouse and keyboard, and the controller chips. Often certain ranges of I/O addresses are reserved for certain types of peripherals, such as graphics, disks, and parallel ports. Thus the number of I/O addresses available to a peripheral controller chips is often limited.
As new features are added to a controller chip, additional registers are needed to control these features. The number of registers needed can quickly exceed the number of discrete addresses in the peripheral's I/O range. I/O addresses are often shared among many registers by using an indexing scheme.
Many registers on a controller chip can be accessed through a pair of I/O addresses using an index register. Registers are accessed in a two-step process. First the microprocessor writes the register's index into a first I/O address, the index register. The controller chip reads the register's index and then couples that register to the chip's input and output. In the second cycle, the microprocessor reads or writes a second I/O address, the data register. The data read or written to the data register is coupled to the register selected by the index written in the first cycle. Other registers on the controller chip can be read or written by writing a different value for the index in the first cycle.
Each access of an indexed register on the controller chip thus takes two cycles rather than just one. First the index is written, then the register identified by the index is accessed. While this slows performance, often the index registers are only infrequently used and thus overall system performance is not hampered. Some registers that are more-frequently accessed can be assigned their own I/O addresses, while other less-frequently-accessed registers can be indexed, sharing the index and data I/O addresses.
Indexed Registers—
FIG. 1
FIG. 1
shows a computer system with a controller chip having indexed registers. A central processing unit (CPU)
12
is a microprocessor that executes instructions in a program stored in memory
14
or in a BIOS ROM (not shown). Display
16
is controlled by graphics controller
10
. Programs executing on CPU
12
can update the information shown on display
16
by writing to a frame buffer inside or controlled by graphics controller
10
. Graphics controller
10
reads lines of pixels from the frame buffer and transfers them to display
16
, which can be a cathode-ray tube (CRT) monitor or a flat-panel display. Bus
11
connects CPU
12
and graphics controller
10
, and includes an address bus and a data bus. Bus
11
may be divided into separate sections by buffer chips.
Graphics controller
10
includes indexed registers
20
that control various features. For example, power-saving modes, display characteristics, timing, and shading can be controlled by CPU
12
writing to indexed registers
20
.
FIG. 2
highlights an index register that selects a data register for access. During a first access cycle, the CPU writes an index to index register
32
. This index is decoded by selector
34
, which selects one of the registers in indexed register
20
for access. The other indexed registers are deselected and cannot be accessed until a new index is written to index register
32
.
In the second CPU access cycle, the CPU writes a data value to a second I/O address. The data written by the CPU is written through selector
34
to the register in indexed registers
20
that was selected by the index in index register
32
. The CPU may also read the selected register rather than write the selected register since selector
34
provides a bi-directional data path, depending on the read/write control signal from the CPU.
The values written to indexed registers
20
are used to control features of the controller chip. For example, indexed registers
20
can output a number of pixels per horizontal line, and a number of lines in a screen, to counters
38
in a graphics controller. When the number of pixels written to the display matches the value of pixels/line from indexed registers
20
, then a horizontal sync HSYNC pulse is generated. When the number of lines counted matches the total number of lines from indexed registers
20
, then the vertical sync VSYNC is generated. Controls for windows within a screen can likewise come from indexed registers
20
, such as for a movie window as described in “Transparent Blocking of CRT Refresh Fetches During Video Overlay Using Dummy Fetches”, U.S. Pat. No. 5,754,170 by Ranganathan et al., and assigned to NeoMagic Corp.
FIG. 3
shows an index-register decoder in a controller chip. I/O address or port
22
(hexadecimal, or hex) is used as the index register, while I/O address
23
(hex) is used for the data register. The CPU first writes the index of the desired register to the index register by executing an I/O output instruction with an address of
22
and the index as the data. Comparator
19
detects that the address matches
22
, the index register, which is ANDed by gate
17
with a strobe generated by logic
21
when the access cycle is for an I/O address rather than a memory address. In the second access cycle, the CPU writes to the data register's port, address
23
. Comparator
18
detects address
23
, and outputs a one to AND gate
15
. When a strobe is generated by logic
21
, AND gate
15
pulses its output REG_ACC, which strobes the data into the selected index register.
FIG. 4
illustrates in an abstract way how an index register and a data register are used to access indexed registers. Index register
32
is accessed when the CPU writes to I/O address
22
, while data register
36
is accessed when the CPU accessed I/O address
23
. Data register
36
does not have to be a physical register, since it merely appears to the CPU to be an I/O port.
During a first cycle, the CPU executes the output instruction out(indx_reg, indx), which sends the address “indx_reg” (
22
hex) out on the address bus, and sends the index “indx” as the data over the data bus. The address “indx_reg” selects index register
32
, while the data “indx” is written into index register
32
. This index is used to select one of the registers in indexed registers
20
for access, coupling the selected register
Auvinen Stuart T.
Chauhan Ulka J.
NeoMagic Corp.
LandOfFree
Closed-loop reading of index registers using wide read and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Closed-loop reading of index registers using wide read and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Closed-loop reading of index registers using wide read and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2559924