Closed loop diode emulator for DC-DC converter

Details Closed loop diode emulator for DC-DC converter Closed loop diode emulator for DC-DC converter

2002-08-21

2004-11-09

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S283000, C323S284000

Reexamination Certificate

active

06815936

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to power supply circuits and components therefor, and is particularly directed to a diode emulator for a DC—DC converter in Discontinuous Conduction Mode (DCM). Prior to each PWM cycle, a tristate pulse (TriState, both switching devices are in the off state) is applied and the phase voltage polarity is sensed. The TriState pulse width is set by a closed loop circuit, and thereby incrementally adjusting the turn-off time of the commutating device according to the polarity of the phase voltage. As a result, it will effectively track the negative going, zero-crossing of the ripple current through the inductor and thereby effectively minimize loss of efficiency.
BACKGROUND OF THE INVENTION
FIG. 1
diagrammatically illustrates the general circuit configuration of a conventional DC—DC voltage buck converter as comprising a DC—DC controller
10
, which switchably controls the turn-on and turn-off of a pair of electronic power switching devices, respectively shown as an upper FET (P-MOSFET or N-MOSFET) device
20
and a lower FET (N-MOSFET) device
30
. These MOSFET switching devices have their drain-source paths coupled in series between first and second reference voltages (Vdd and ground (GND)). A common or phase voltage node
25
between the two power FETs
20
/
30
is coupled through an inductor
40
(which may typically comprise a transformer winding) to a capacitor
50
coupled to a reference voltage terminal (GND). The connection
45
between the inductor
40
and the capacitor
50
serves as an output node from which an output voltage Vout is derived.
The buck converter's DC—DC controller
10
includes a gate driver circuit
11
, that is operative to controllably turn the two switching devices
20
and
30
on and off, in accordance with a pulse width modulation (PWM) switching waveform (such as that shown at PWM in the timing diagram of
FIG. 2
) generated by a PWM logic circuit
12
. The upper FET device
20
is turned on and off by an upper gate switching signal UG applied by the gate driver
11
to the gate of the upper FET device
20
, and the lower FET device
30
is turned on and off by a lower gate switching signal LG applied by the gate driver
11
to the gate of the lower FET device
30
.
For the case of timing diagram of
FIG. 2
, the upper FET
20
is turned on in accordance with the rising edge of the PWM waveform and turned off in accordance with the falling edge of the PWM waveform, whereas the lower NFET
30
is turned on in accordance with the falling edge of the PWM waveform. During relatively light load conditions, where the ripple current IL through the inductor
40
is larger than the average inductor current, it is desired to revert to a basic DC—DC converter. This is effected by effectively replacing the lower switching FET
30
with a diode function—optimally turning off the lower switching device coincident with the negative-going zero-crossing of the inductor ripple current IL, so as to prevent current return flow back into the converter, and maximizing efficiency.
Prior art techniques to accomplish this diode transition operation may sense the ripple current flowing through the inductor
40
via node
45
, or may sense the phase voltage at node
25
and couple the sensed variation to a comparator.
FIG. 1
shows the example where the phase node voltage Vp is coupled to a comparator
13
. Ideally, the comparator, which is enabled by the PWM logic circuit, will provide an output coincident with the negative-going, zero-crossing of the ripple current, in response to which the controller's output driver turns off the lower NFET switch.
Unfortunately, this technique is successful only at relatively low PWM frequencies, due to the propagation delay through the comparator. To obtain reasonably acceptable performance at relatively high PWM frequencies (e.g., on the order of 1 MHZ and above), it is necessary to use a comparator that requires a large current, which increases cost and is not practical for low power applications.
SUMMARY OF THE INVENTION
In accordance with the present invention, shortcomings of DC—DC buck converter diode emulators, including those described above, are effectively obviated by means of a variable current ramp-based diode emulator, that monitors the state of the phase voltage at the common node between the two switching devices and, incrementally with each PWM cycle, adjusts the turn-off time of the lower FET, until the monitored phase voltage indicates that the emulator is effectively tracking the negative going, zero-crossing of the ripple current through the inductor.
For this purpose, the diode emulator includes a phase voltage sample circuit that is coupled to receive a tristate pulse signal and a phase voltage signal. The tristate pulse signal starts just after turning-off the lower FET and prior to the front edge of the PWM pulse signal and terminates at the start of the PWM pulse. The phase voltage is derived from the common node between the two FETs. The rate at which the phase voltage Vp changes during the interval of the tristate pulse depends upon the properties of the FETs and inductor current. Due to the inherent body diode properties of the upper and lower FET switches and the properties of the inductor, the phase voltage will have a relatively positive edge at the tristate pulse if the lower FET is turned off too late. If the lower FET is turned off too early, however, the phase voltage remains low, being sensed as a second logical state.
The sensed phase voltage sample is coupled to the data input of a multibit up/down counter, which is sequentially clocked by the PWM signal. The up/down counter is used to control the rate of discharge of a lower power FET turn-off control capacitor, and thereby the time of occurrence of a turn-off signal for the lower FET, based upon whether the lower FET was turned-off too early or too late during the previous PWM cycle.
At each PWM pulse, the contents of up/down counter are either incremented or decremented, depending on the state of phase voltage as sampled/sensed by the TriState pulse. For a first binary state of the sensed phase voltage, indicating that in the previous cycle the lower power FET was turned off too late, the contents of the up/down counter will be ‘incremented’ by one bit at the next PWM pulse. For a second binary state of the sense phase voltage, indicating that in the previous cycle the lower power FET was turned off too early, the contents of the up/down counter are ‘decremented’ by one bit at the next PWM pulse.
The digital outputs of the up/down counter are coupled to relay drive inputs of relay coils of a set of relay switches. The switch contacts of the relay switches are coupled between to a charge/discharge node of the lower power FET turn-off control capacitor and outputs of a multiport current mirror. The current mirror has a further output coupled to the charge/discharge node of the lower power FET turn-off control capacitor, and is configured such that the currents at its output ports are binarily weighted in accordance with preselected weighting ratios relative to a reference input current.
This selective weighting of the mirror's output currents is defined in accordance with a prescribed capacitor discharge transfer function and serves to provide an adjustable (variable slope) ramp signal to a first input of a digital comparator. A second input of the digital comparator is coupled to receive the voltage VREF (
308
in FIG.
3
). The output of the digital comparator is coupled via a flip-flop to an output port, from which the lower FET turn-off signal is supplied to the controller.
In response to the tristate pulse signal, the phase voltage sample circuit senses the state of the phase voltage. As pointed out above, the phase voltage will produce a relatively high positive edge if the lower NFET is turned off too late, whereas if the lower NFET is turned off too early, the phase voltage will remain low. The sensed ‘digital’ state of the phase voltage is coupled to the u

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