Closed loop clock recovery for synchronous residual time stamp

Details Closed loop clock recovery for synchronous residual time stamp Closed loop clock recovery for synchronous residual time stamp

1995-03-31

1997-03-04

Olms, Douglas W.

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

370518, 370395, 375376, H04L 708

Patent

active

056087314

ABSTRACT:
An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.

REFERENCES:
patent: 4961188 (1990-10-01), Lau
patent: 5007070 (1991-04-01), Chao et al.
patent: 5204882 (1993-04-01), Chao et al.
patent: 5260978 (1993-11-01), Fischer et al.
patent: 5396492 (1995-03-01), Lien
"Adaptive Clock Synchronization Schemes for Real Time Traffic in Broadband Packet Networks", Singh et al., Bell Communications Research.
"Jitter and Clock Recovery for Periodic Traffic in Broadband Packet Networks", Singh et al., Bell Communications Research, Inc.
"Jitter Reduction in ATM Networks", Gonzales et al. Centre National D'Etudes des Telecommunications, France, 1991.

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