Closed-grid bus architecture for wafer interconnect structure

Details Closed-grid bus architecture for wafer interconnect structure Closed-grid bus architecture for wafer interconnect structure

2003-04-02

2004-08-31

Karlsen, Ernest F. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

06784677

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an interconnect structure for providing signal paths between test equipment and contact pads on a semiconductor wafer, and in particular to a wafer interconnect structure employing a closed-grid bus to distribute signals to several integrated circuit devices under test.
2. Description of Related Art
In many applications microstrip or stripline traces convey a logic signal from a single source to many nodes on a printed circuit board (PCB). For example traces on a motherboard commonly distribute data, address and control lines of computer buses to sockets holding daughterboards, or traces on a PCB may distribute a clock signal to several synchronously operating integrated circuits (ICs) mounted on the PCB.
A typical integrated circuit (IC) tester includes a test head structure containing a set of tester channels. Each tester channel may either transmit a test signal to an IC input/output (I/O) terminal or monitor a IC output signal appearing at an IC I/O terminal to determine whether the IC is behaving as expected in response to its input signals. When ICs are tested while still in the form of die on a semiconductor wafer, a “prober” typically holds a wafer adjacent to the test head and provides a set of probes contacting I/O pads of one or more ICs. An interconnect structure is provided to link the tester channels to the probes. A typical interconnect structure includes a circuit board having upper and lower surfaces containing contact pads. A separate pogo pin extending from each tester channel contacts a separate one of the upper surface contact pads. An “interposer” mounted between the circuit board and the prober includes spring contacts linking the contact pads on the lower surface of the circuit board to the probes. Traces on various layers of the circuit board, and vias interconnecting those traces provide appropriate signal paths between the upper and lower contact pads.
Normally the interconnect structure links each tester channel to only a single I/O pad of a single IC. However in some cases, for example when a tester channel is supplying power to ICs under test, the interconnect structure may connect a single channel to more than power supply pad.
Since there are usually more I/O pads than available tester channels, an IC tester can test only a portion of the ICs on the wafer at any one time. Thus the “prober” holding the wafer must reposition the wafer under the probes several times so that all ICs can be tested. It would be advantageous if all ICs on a wafer could be contacted and tested concurrently without having to reposition the wafer.
One way to reduce the number of tester channels needed to do this is to concurrently connect the same tester channel to corresponding I/O pads of a large number of ICs on the wafer. For example an IC tester tests a random access memory (RAM) by writing data into each RAM address, reading it back out, and determining whether the data read out of the RAM matches the data written into it. When the tester has a sufficient number of channels to separately access I/O pads of more than one RAM, it can independently test several RAMs concurrently.
However it is also possible for a tester to concurrently test several RAMs without requiring so many tester channels by connecting the data and address I/O pads of several RAMs in parallel to the same set of tester channels while connecting the control I/O pads of the RAMs to separate tester channels. This arrangement enables the tester to concurrently write access several RAMs while allowing it to consecutively read access each RAM. The arrangement therefore reduces the number of write cycles needed to test the RAMs, substantially reduces the number of channels needed to concurrently test all of the RAMs on the wafer, and eliminates the need to position the wafer under the interconnect structure more than once. Thus instead of providing a set of signal paths, each connecting a single tester channel to a single IC pad, an interconnect structure for a wafer-level tester could provide a set of buses, each providing a path from a single tester channel to a large number probes accessing IC pads.
When such buses are formed by traces on a printed circuit board (PCB) each bus should make efficient use of PCB area since many buses must share a relatively small amount of PCB area above each IC. Also each bus should deliver the signal to ICs with as little variation in edge timing as possible and with as little distortion as possible.
Logic signals have been commonly distributed to many nodes on a PCB using stripline or microstrip traces in a “daisy-chain”, or “star” or “stubbed” bus configurations.
FIG. 1
illustrates a conventional daisy-chain bus configuration wherein traces
10
on a PCB
12
connect a set of bus nodes
14
in series to route an incoming signal (IN) to each bus node. The daisy-chain configuration makes efficient use of PCB space. However since each IN signal edge must travel a relatively large distance between the first and last nodes
13
and
15
, and must charge IC input capacitance as it arrives at several intermediate nodes
14
, the time difference between detection of IN signal edges by ICs connected to nodes
13
and
15
can be relatively large. A long-daisy chain bus can also severely distort the signal wave front as it passes from node-to-node; the last node on the bus will see substantially slower rise time than the first. Such wave front distortion tends to increase the variation in signal path delay between the first and last nodes
13
and
15
on the daisy-chain bus.
A daisy-chain bus is also intolerant of open-circuit faults; an open circuit fault anywhere on the daisy-chain bus will prevent the signal from reaching any node beyond the fault. Since an interconnect structure for a wafer-level tester would have a large number buses formed by small traces, since each bus would include a large number of nodes on each bus, and since each bus would be implemented by small traces, there would be many places on the bus were a fault could occur, and any one fault would render the interconnect structure unsuitable for use in a wafer-level tester interconnect system since several ICs on each wafer would be untestable.
FIG. 2
illustrates a star bus in which the incoming signal is directly linked to each node
14
by a separate trace
16
. A star bus has a number of advantages over a daisy-chain bus. Though not apparent in
FIG. 2
, when all traces
16
are of similar length, input signal edges will arrive at all nodes
14
at substantially the same time. A star bus distorts and attenuates signals less than a daisy-chain bus, and every node
14
sees substantially the same wave front shape. A star bus is also relatively more tolerant of open circuit faults than a daisy-chaining bus since an open circuit on any trace
16
will prevent the signal for reaching only one node
14
. However even a single open circuit fault would none-the-less render an interconnect structure employing a star bus unsuitable in a wafer-testing because it would mean that one IC on each wafer would be untestable. Also since a star bus requires substantial amounts of circuit board space, it would be unsuitable as a bus in an interconnect structure for a wafer-level IC tester where a large number of buses would be concentrated into a small area.
FIG. 3
illustrates a prior art stubbed bus arrangement. The stubbed bus of
FIG. 3
includes a core daisy-chain bus
20
and several daisy-chain branch buses or “stubs”
18
. Each stub
18
has a proximal end connected to core bus
20
and a distal end remote from core bus
20
. The traces of stubbed bus of
FIG. 3
use about the same amount of PCB space as the daisy-chain bus of
FIG. 1
, but the stubbed bus substantially reduces variation in timing of signal edges arriving at its nodes because it reduces the variation in signal path distance the incoming signal must travel in reaching the nearest and most distant nodes
21
and
22
.
The stubbed bus arrangement is

Affiliated with

Also associated with

Rating

Closed-grid bus architecture for wafer interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Closed-grid bus architecture for wafer interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Closed-grid bus architecture for wafer interconnect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3317266