Closed-grid bus architecture for wafer interconnect structure

Details Closed-grid bus architecture for wafer interconnect structure Closed-grid bus architecture for wafer interconnect structure

2011-06-14

2011-06-14

Nguyen, Vinh P (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754030

Reexamination Certificate

active

07960990

ABSTRACT:
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

REFERENCES:
patent: 3068403 (1962-12-01), Robinson
patent: 3458807 (1969-07-01), Smith
patent: 3821645 (1974-06-01), Vinsani
patent: 4281449 (1981-08-01), Ports et al.
patent: 4290015 (1981-09-01), Labriola
patent: 4791363 (1988-12-01), Logan
patent: 4853624 (1989-08-01), Rabjohn
patent: 4862077 (1989-08-01), Horel et al.
patent: 4894612 (1990-01-01), Drake et al.
patent: 4968931 (1990-11-01), Littlebury et al.
patent: 4994735 (1991-02-01), Leedy
patent: 5012187 (1991-04-01), Littlebury
patent: 5086271 (1992-02-01), Haill et al.
patent: 5148103 (1992-09-01), Pasiecznik, Jr.
patent: 5219765 (1993-06-01), Yoshida et al.
patent: 5237268 (1993-08-01), Honma et al.
patent: 5241266 (1993-08-01), Ahmad et al.
patent: 5294776 (1994-03-01), Furuyama
patent: 5307010 (1994-04-01), Chiu
patent: 5397997 (1995-03-01), Tuckerman et al.
patent: 5399505 (1995-03-01), Dasse et al.
patent: 5442282 (1995-08-01), Rostoker et al.
patent: 5444366 (1995-08-01), Chiu
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5497079 (1996-03-01), Yamada et al.
patent: 5497379 (1996-03-01), Whetsel
patent: 5532614 (1996-07-01), Chiu
patent: 5541524 (1996-07-01), Tuckerman et al.
patent: 5548223 (1996-08-01), Cole et al.
patent: 5576630 (1996-11-01), Fujita
patent: 5592632 (1997-01-01), Leung et al.
patent: 5594273 (1997-01-01), Dasse et al.
patent: 5608335 (1997-03-01), Tailliet
patent: 5608337 (1997-03-01), Hendricks et al.
patent: 5623214 (1997-04-01), Pasiecznik, Jr.
patent: 5654588 (1997-08-01), Dasse et al.
patent: 5654647 (1997-08-01), Uhling et al.
patent: 5682472 (1997-10-01), Brehm et al.
patent: 5689515 (1997-11-01), Panis
patent: 5701666 (1997-12-01), DeHaven et al.
patent: 5736850 (1998-04-01), Legal
patent: 5794175 (1998-08-01), Conner
patent: 5852581 (1998-12-01), Beffa et al.
patent: 5872459 (1999-02-01), Pasiecznik, Jr.
patent: 5894484 (1999-04-01), Illes et al.
patent: 5898312 (1999-04-01), Uhling et al.
patent: 5917329 (1999-06-01), Cadwallader et al.
patent: 5952838 (1999-09-01), Tikhonov
patent: 5990696 (1999-11-01), Swart
patent: 5995915 (1999-11-01), Reed et al.
patent: 6047469 (2000-04-01), Luna
patent: 6064213 (2000-05-01), Khandros et al.
patent: 6078187 (2000-06-01), Hanners et al.
patent: 6107815 (2000-08-01), Nikutta et al.
patent: 6107818 (2000-08-01), Czamara
patent: 6228684 (2001-05-01), Maruyama
patent: 6275962 (2001-08-01), Fuller et al.
patent: 6351134 (2002-02-01), Leas et al.
patent: 6603323 (2003-08-01), Miller et al.
patent: 6622103 (2003-09-01), Miller
patent: 6703854 (2004-03-01), Hashimoto
patent: 6784674 (2004-08-01), Miller
patent: 6784677 (2004-08-01), Miller et al.
patent: 6812691 (2004-11-01), Miller
patent: 6917214 (2005-07-01), Farber et al.
patent: 7276922 (2007-10-01), Miller et al.
patent: 7508227 (2009-03-01), Miller et al.
patent: 2009/0179659 (2009-07-01), Miller et al.
patent: 3637502 (1988-05-01), None
patent: 61099876 (1986-05-01), None
patent: 06027195 (1994-02-01), None
patent: WO 00/39848 (2000-07-01), None
patent: WO 00/52487 (2000-09-01), None
patent: WO 00/52488 (2000-09-01), None
“N-UP Test Adapter”, IBM Technical Disclosure Bulletin, Publication No. XP 000627991, vol. 39, No. 7, Jul. 1996.

Affiliated with

Also associated with

Rating

Closed-grid bus architecture for wafer interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Closed-grid bus architecture for wafer interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Closed-grid bus architecture for wafer interconnect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2666700