Closed cell configuration to increase channel density for...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means

Reexamination Certificate

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Details

C257S204000, C257S205000, C257S207000, C257S208000, C257S211000, C257SE27060, C257SE27081

Reexamination Certificate

active

07956384

ABSTRACT:
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.

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patent: 5517046 (1996-05-01), Hsing et al.
patent: 6069396 (2000-05-01), Funaki
patent: 6140687 (2000-10-01), Shimomura et al.
patent: 6287922 (2001-09-01), Yu et al.
patent: 6388292 (2002-05-01), Lin
patent: 6818950 (2004-11-01), Mallikararjunaswamy

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