Clockless serialization using delay circuits

Coded data generation or conversion – Digital code to digital code converters – Parallel to serial

Reexamination Certificate

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C327S408000

Reexamination Certificate

active

07468685

ABSTRACT:
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing alignment of the data bit and the timing signal. No clock is used. This allows the deserialzer/receiver to reliably receive the data bit. Each illustrative delay circuit is configured to trigger the next register/delay circuit to output the next sequential bit and its timing signal.

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patent: 2004/0201411 (2004-10-01), White

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