Coded data generation or conversion – Digital code to digital code converters – Parallel to serial
Reexamination Certificate
2007-08-20
2008-12-23
Williams, Howard (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Parallel to serial
C327S408000
Reexamination Certificate
active
07468685
ABSTRACT:
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing alignment of the data bit and the timing signal. No clock is used. This allows the deserialzer/receiver to reliably receive the data bit. Each illustrative delay circuit is configured to trigger the next register/delay circuit to output the next sequential bit and its timing signal.
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Cesari and McKenna LLP
Fairchild Semiconductor Corporation
Paul, Esq. Edwin H.
Williams Howard
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